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US 2003/0170934 A1Published application
Top layers of metal for high performance IC's
AssigneeMegic Corporation
InventorMou-Shiung Lin
Life of this patent
Estimating the term…
Abstract
A method of closely interconnecting integrated circuits contained within a semiconductor wafer to electrical circuits surrounding the semiconductor wafer. Electrical interconnects are held to a minimum in length by making efficient use of polyimide or polymer as an inter-metal dielectric thus enabling the integration of very small integrated circuits within a larger circuit environment at a minimum cost in electrical circuit performance.
Claims79
A method for forming a top metalization system for high performance integrated circuits, comprising:
- forming an integrated circuit comprising a plurality of devices formed in and on a semiconductor substrate, with an overlaying interconnecting metalization structure connected to said devices and comprising a plurality of first metal lines in one or more layers;
- depositing a passivation layer over said interconnecting metalization structure;
- depositing an insulating, separating layer over said passivation layer that is substantially thicker than said passivation layer;
- forming openings through said insulating, separating layer and said passivation layer to expose upper metal portions of said overlaying interconnecting metalization structure;
- depositing metal contacts in said openings;
- and
- forming said top metalization system connected to said overlaying interconnecting metalization structure, wherein said top metalization system comprises a plurality of top metal lines, in one or more layers, each of said top metal lines having a width substantially greater than said first metal lines.
4 more elements
A semiconductor device structure comprising:
- a semiconductor substrate comprising semiconductor devices;
- an interconnecting metalization structure connected to said devices;
- electrical contact points on an upper top surface of said interconnecting metalization structure and connected to said interconnecting metalization structure;
- a passivation layer deposited over said interconnecting metalization structure and over said electrical contact points;
- an insulating layer deposited over said passivation layer said insulating layer being substantially thicker than said passivation layer;
- openings through said insulating layer and through said passivation layer down to the upper surface of said electrical contact points;
- metal conductors within said openings;
- and
- an upper metalization structure connected to said metal conductors.
6 more elements
A method for forming a top metalization system for high performance integrated circuits, comprising:
- forming an integrated circuit comprising a plurality of devices formed in and on a semiconductor substrate, with an overlaying interconnecting metalization structure connected to said devices and comprising a plurality of first metal lines;
- depositing an insulating, separating layer over said semiconductor substrate;
- forming openings through said insulating, separating layer to expose upper metal portions of said interconnecting metalization structure;
- depositing metal contacts in said openings;
- and
- forming said top metalization system connected to said interconnecting metalization structure, wherein said top metalization system comprises a plurality of top metal lines, in one or more layers, having a width substantially greater than said first metal lines.
3 more elements
A method for forming a top metalization system for high performance integrated circuits, comprising:
- forming an integrated circuit comprising a plurality of devices formed in and on a semiconductor substrate, with an overlaying interconnecting metalization structure connected to said devices and comprising a plurality of fine-wire metal lines;
- depositing a passivation layer over said interconnecting fine-wire metalization structure;
- depositing an insulating, separating layer over said passivation layer that is substantially thicker than said passivation layer;
- forming openings through said insulating, separating layer to expose upper metal portions of said overlaying interconnecting metalization structure;
- depositing metal contacts in said openings thereby raising a plurality of contact points in said overlaying interconnecting metalization structure to the top surface of said insulating, separating layer thereby creating elevated interconnecting metalization contact points;
- forming said top metalization system connected to said overlaying interconnecting metalization structure, wherein said top metalization system comprises a plurality of top wide-metal lines, in one or more layers, having a width substantially greater than said fine-wire metal lines, wherein said top metalization system directly interconnects said elevated interconnecting metalization contact points thereby functionally extending or connecting said fine-wire metal interconnects with said wide-wire metal interconnects thereby furthermore establishing electrical interconnects between multiple points within said fine-wire interconnects.
3 more elements
Dependencies are inferred from the claim text.