Methods and apparatus for packaging semiconductor devices
AssigneeMicron Technology, Inc.
InventorTodd O. Bolken
Life of this patent
Estimating the term…
Abstract
A method and apparatus for increasing the integrated circuit density of a thin small outline package (“TSOP”) semiconductor assembly is provided by stacking two semiconductor dice and electrically connecting the substantially centrally located bond pads of substantially identically arranged bond pads of each die the same surface of a single lead frame. Each semiconductor die may be electrically connected to a plated, common connection surface of the lead frame. The lead frame may include downsets to properly position the semiconductor assembly within the package. Further, if wire bonds are used as electrical connection elements, stitch bonding may be employed to enhance rigidity of the bond wires and to modify electrical characteristics of the electrical connection elements.
Claims111
A method for forming a semiconductor device assembly comprising:
- providing a first semiconductor die including substantially centrally located bond pads;
- providing a second semiconductor die including substantially centrally located bond pads;
- providing a lead frame comprising an electrical connection surface;
- securing said first and second semiconductor dice to at least one said lead frame and the other of said first and second semiconductor dice;
- and
- electrically connecting substantially centrally located bond pads of both said first and second semiconductor dice to said electrical connection surface of corresponding lead fingers of said lead frame.
A method for forming semiconductor device assembly comprising:
- providing first and second semiconductor dice having substantially identical bond pad patterns;
- providing a lead frame comprising an electrical connection surface;
- securing said first and second semiconductor dice to at least one said lead frame and the other of said first and second semiconductor dice;
- and
- electrically connecting bond pads of both said first and second semiconductor dice to said electrical connection surface of corresponding lead fingers of said lead frame.
A semiconductor device assembly, comprising:
- a first semiconductor die including substantially centrally located bond pads;
- a second semiconductor die including substantially centrally located bond pads;
- a lead frame comprising an electrical connection surface and a plurality of lead fingers, each including a portion of said electrical connection surface;
- and
- a plurality of electrical connection elements between bond pads of said first and second semiconductor devices and said portions of said electrical connection surface on corresponding lead fingers of said plurality of lead fingers.
A semiconductor device assembly, comprising:
- first and second semiconductor dice including bond pads arranged in substantially identical connection patterns;
- a lead frame comprising an electrical connection surface and a plurality of lead fingers, each including a portion of said electrical connection surface;
- and
- a plurality of electrical connection elements between bond pads of said first and second semiconductor devices and corresponding portions of said electrical connection elements on lead fingers of said plurality of lead fingers.
A method for designing a thin small outline package comprising:
- configuring a lead frame with a single connection surface;
- selecting first and second semiconductor dice that include substantially centrally located bond pads;
- configuring a first plurality of electrical connection elements to extend between substantially centrally located bond pads of said first semiconductor die and said connection surface of said lead frame;
- and
- configuring a second plurality of electrical connection elements between substantially centrally located bond pads of said first semiconductor die and said connection surface of said lead frame.
A method for designing a thin small outline package comprising:
- configuring a lead frame with a single connection surface;
- selecting first and second semiconductor dice that include bond pads arranged in substantially identical connection patterns;
- configuring a first plurality of electrical connection elements to extend between bond pads of said first semiconductor die and said connection surface of said lead frame;
- and
- configuring a second plurality of electrical connection elements between bond pads of said first semiconductor die and said connection surface of said lead frame.
Dependencies are inferred from the claim text.