EMI reduction using tunable delay lines

The circuit according to claim 7, wherein the delay generator further comprises a delay multiplexer having two inputs and an output;

• and
• wherein the delay circuit further comprises a first delay line and a second delay line;
• wherein the first delay line is coupled to one input of the delay multiplexer and the second delay line is coupled to the other input of the delay multiplexer;
• wherein the delay controller is capable of separately controlling the first delay line and the second delay line;
• and
• wherein the delay controller controls the delay multiplexer to select either one of the first and second delay lines to drive the output of the delay multiplexer.

A clock-signal-delaying circuit, comprising:

• a first adjustable delay line having a clock signal as its input;
• a second adjustable delay line having the clock signal as its input;
• a delay multiplexer having two inputs and an output, wherein the first and second adjustable delay lines are respectively coupled to the two inputs;
• and
• a delay controller for controlling the first and second adjustable delay lines and the delay multiplexer in accordance with a control signal;
• wherein the control signal represents an overall delay of the clock signal;
• wherein the delay multiplexer selects either the first adjustable delay line or the second adjustable delay line in accordance with a command generated by the delay controller to drive its output to produce a delayed version of the clock signal;
• and
• wherein the overall delay varies with time in such a manner as to cause spreading of the spectrum of the delayed version of the clock signal.

An improved clock-signal-generating circuit, comprising:

• a reference oscillator for generating a first clock signal;
• a frequency multiplier for increasing the frequency of the first clock signal thereby producing a second clock signal;
• and
• a clock buffer for amplifying the second clock signal;
• wherein the circuit is improved by including a delay element coupled between the frequency multiplier and the clock buffer;
• and
• wherein the delay element phase-modulates the second clock signal produced by the frequency multiplier in accordance with a predetermined delay.

A method for reducing electromagnetic interference generated by a signal inside an electronic device, comprising the steps of:

• generating the signal;
• phase-modulating the signal in accordance with a control delay;
• and
• routing the phase-modulated signal to logic circuitry located within the electronic device;
• wherein the step of phase-modulating the signal results in a spreading of the energy of the signal over a range of frequencies in a short time interval.

An improved method for reducing electromagnetic interference generated by a clock signal, comprising the steps of:

• generating a first clock signal;
• multiplying the frequency of the first clock signal to produce a second clock signal;
• and
• amplifying the second clock signal before distributing the second clock signal to logic circuitry;
• wherein said improvement comprises the step of:
• phase-modulating the second clock signal before the amplifying step;
• wherein the step of phase-modulating the second clock signal results in a spreading of the energy of the second clock signal over a range of frequencies;
• and
• wherein the spreading of the energy of the second clock signal over the range of frequencies is achieved over a short time interval.

A clock-signal-delaying circuit, comprising:

• a plurality of adjustable delay lines each having a clock signal as its respective input;
• a delay multiplexer having a plurality of inputs and an output, wherein the plurality of adjustable delay lines are respectively coupled to the plurality of inputs;
• and
• a delay controller for controlling the plurality of adjustable delay lines and the delay multiplexer in accordance with a control signal;
• wherein the control signal represents an overall delay of the clock signal;
• wherein the delay multiplexer selects one of the plurality of adjustable delay lines in accordance with a command generated by the delay controller to drive its output to produce a delayed version of the clock signal;
• and
• wherein the overall delay varies with time in such a manner as to cause spreading of the spectrum of the delayed version of the clock signal.