Timing recovery with variable bandwidth phase locked loop and non-linear control paths

A timing recovery system to receive input data having a phase, comprising:

• a phase locked loop to lock a phase of a local clock to the phase of said input data, said phase locked loop receiving said input data and generating a phase locked loop output;
• a first proportional path with non-linear control to adjust the phase of said input data in response to a data pattern of said input data, said first proportional path receiving said input data and generating a first proportional path output;
• a second proportional path with non-linear control to adjust the phase of said input data in response to an amplitude of data samples from said input data, said second proportional path receiving said input data and generating a second proportional path output;
• and
• a system summing node, wherein said phase locked loop output, said first proportional path output, and said second proportional path output are summed by said system summing node to generate a system summing node output.

A timing recovery system, comprising:

• a machine-readable storage medium;
• and
• machine-readable program code, stored on the machine-readable storage medium, the machine-readable program code having instructions to:
• estimate a phase error based on a data sample from both a center of a data eye of input data and from a phase sample from said input data half-a-baud later in time;
• correlate said phase error with a sign of recovered data;
• filter said correlated phase error by a loop filter to generate an output;
• sum said output with a path output from at least one non-linear path to generate a summed output;
• and
• convert said summed output into clock phase information.

A receiver system, comprising:

• a receiver circuit;
• an antenna in electronic communication with said receiver circuit;
• and
• a timing recovery system circuit in electronic communication with said receiver circuit.