Phase comparator and clock recovery circuit

A clock recovery circuit generating a clock signal from a supplied data signal, comprising:

• a frequency divided signal-generating means for generating a first frequency divided signal from the data signal and a second frequency divided signal whose phase is different from that of the first frequency divided signal;
• a first phase comparator receiving as input the first frequency divided signal, and intermittently performing a phase comparison between either one of a rising edge or a falling edge of the data signal and the clock signal according to the logic level of the first frequency divided signal;
• and
• a second phase comparator receiving as input the second frequency divided signal, and intermittently performing a phase comparison between the other one of the rising edge or the falling edge of the data signal and the clock signal according to the logic level of the second frequency divided signal.

A clock recovery circuit generating a clock signal from a supplied data signal, comprising:

• a frequency divided signal-generating means for generating a first frequency divided signal from the data signal and a second frequency divided signal whose phase is different from that of the first frequency divided signal;
• a first phase comparator receiving as input the first frequency divided signal, and intermittently performing a phase comparison between the data signal and the clock signal according to the logic level of the first frequency divided signal;
• and
• a second phase comparator receiving as input the second frequency divided signal, and intermittently performing a phase comparison between the data signal and the clock signal according to the logic level of the second frequency divided signal;
• wherein the frequency divided signal-generating means generates the second frequency divided signal so that the timing of the phase comparison of the first phase comparator is shifted from the timing of the phase comparison of the second phase comparator.