Error correction method and apparatus for data transmission system

A decision system in high-speed data transmission, comprising:

• a data decision circuit to determine a value of an input signal at a decision instance and to hold the value as a tentative value;
• an error estimator module to determine an error value of the value, to amplify the error value, and to hold the amplified error value as a corrected value,
• an error verifier module to determine whether the amplified error value is within a marginal range;
• a transition detecting module, to determine whether the input signal was in transition from a positive to negative state, or a negative to positive state during a symbol period;
• and
• an error correction module to determine whether the tentative value should be overridden by the corrected value.

A receiver utilized in high speed data transmission to output data values, comprising:

• an analog-to-digital converter to receive an input signal and to output a sampled digital signal and a phase information;
• a decision system to receive the sampled digital signal and to output a value from the receiver, wherein the decision system:
• receives the sampled digital signal, calculates a value at a decision instance, and assigns a tentative value;
• calculates an error value, amplifies the error value and holds it as a corrected value;
• determines if the error value is within a marginal range;
• determines whether the input signal was in a transition from a positive to negative state, or a negative to positive state during a symbol period;
• and
• outputs the corrected value as the value if the error value is within the marginal range and if the input signal is in a transition during a symbol period;
• a phase detector to receive the value and the phase information and to output a detected phase information;
• a loop filter to receive the detected phase information and to output a filtered phase information;
• and
• an oscillator to receive the filtered phase information and to output a clock signal as a sampling clock for the analog-to-digital converter.

A decision circuit, comprising:

• a machine-readable storage medium;
• and
• machine-readable program code, stored on the machine readable storage medium, the machine-readable program code having instructions to
• calculate a value of an input signal at a decision instance and to hold the value as a tentative value,
• calculate an error value, amplify the error value, and hold the amplified error value as a corrected value,
• determine whether the error value is within a marginal range,
• determine the input signal was in transition from a positive to negative state, or from a negative to positive state during a symbol period, and
• decide whether the tentative value should be overridden by the corrected value.