Method and apparatus for reducing latency in a digial signal processing device

In a digital signal processing device including delay generation circuitry and processing circuitry coupled to the delay generation circuitry, a method for processing an input signal presented to the digital signal processing device, the method comprising the steps of:

• identifying a first subset of signal paths through the delay generation circuitry, the first subset of signal paths including a zero delay signal path;
• identifying at least a second subset of signal paths through the delay generation circuitry, the second subset of signal paths including one or more nonzero delay signal paths;
• operatively removing an idle delay from all signal paths in the second subset, such that a shortest nonzero delay signal path in the second subset becomes a zero delay signal path;
• and
• incorporating the idle delay with the processing circuitry.

Apparatus for processing an input signal, the apparatus comprising:

• a memory, the memory being capable of storing one or more delayed samples of the input signal;
• and
• at least one processor coupled to the memory, the at least one processor being operative to:
• (i) identify a first subset of signal paths through the memory, the first subset of signal paths including a zero delay signal path;
• (ii) identify at least a second subset of signal paths through the memory, the second subset of signal paths including one or more nonzero delay signal paths;
• (iii) operatively remove an idle delay from all signal paths in the second subset, such that a shortest nonzero delay signal path in the second subset becomes a zero delay signal path;
• and (iv) merge the idle delay into the at least one processor.

An integrated circuit (IC) device, the IC device including at least one digital signal processing device for processing an input signal, the at least one digital signal processing device comprising:

• delay generation circuitry, the delay generation circuitry including an input for receiving the input signal and a plurality of delay stages operatively coupled together, each of the delay stages having a predetermined time delay associated therewith, the delay generation circuitry including a zero delay signal path and at least one nonzero delay signal path associated therewith;
• and
• processing circuitry coupled to the delay generation circuitry, the processing circuitry being operatively configured to:
• (i) define a first subset of signal paths through the delay generation circuitry, the first subset including the zero delay signal path, and at least a second subset of signal paths through the delay generation circuitry, the second subset including one or more nonzero delay signal paths;
• (ii) remove an idle delay from all signal paths in the second subset, such that a shortest nonzero delay signal path in the second subset becomes a zero delay signal path;
• and (iii) incorporate the idle delay with the processing circuitry.