US 2003/0169773 A1 · Desynchronizer having ram based shared digital phase locked loops and sonet high density demapper incorporating same

Abstract

A SONET demapper includes three desynchronizers, each of which includes a RAM-based, shared digital phase locked loop, shared elastic storage, and twenty-eight divide-by 33/34/44/45 counters. Unlike a conventional desynchronizer which uses separate FIFOs for each of the twenty-eight T1/E1 channels, the elastic storage for each channel is an addressed portion of a shared block of RAM. Each desynchronizer generates a clock for each of the twenty-eight T1/E1 channels based on a FIFO depth count for each channel which is derived from a read pointer, an “effective write pointer”, and the divide-by clock for the channel. Each desynchronizer can desynchronize both T1 and E1 signals as well as a combination of these signals. In addition, the invention combines the leak FIFO and desynchronizer FIFO into a single FIFO with an effective write pointer. This eliminates the need to maintain separate counters and pointers for separate FIFOs.

Claims24

Dependent claims

A desynchronizer for a SONET demapper, comprising:

a) a data FIFO for storing data for a plurality of channels;
and
b) a plurality of digital phase locked loops coupled to said FIFO for reading data out of said FIFO, said plurality of digital phase locked loops being implemented with shared circuitry for generating FIFO read addresses and a plurality of divide-by counters selectively coupled, one at a time, to said shared circuitry in response to a clock signal.

Dependencies are inferred from the claim text.

Desynchronizer having ram based shared digital phase locked loops and sonet high density demapper incorporating same

Life of this patent

Desynchronizer having ram based shared digital phase locked loops and sonet high density demapper incorporating same

Life of this patent

Abstract

Claims24