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US 2003/0169631 A1Published application
Semiconductor memory device with improved flexible redundancy scheme
AssigneeMitsubishi Denki Kabushiki Kaisha
InventorHideto Hidaka
Life of this patent
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Abstract
A spare memory array having spare memory cells common to a plurality of normal sub-arrays having a plurality of normal memory cells is provided. A spare line in the spare array can replace a defective line in the plurality of normal sub-array. The defective line is efficiently repaired by replacement in an array divided into blocks or sub-arrays.
Claims20
A semiconductor memory device, comprising:
- a plurality of memory blocks each having a plurality of normal memory cells;
- a plurality of spare memory blocks provided corresponding to said plurality of memory blocks each for repairing a defective normal memory cell in a corresponding memory block;
- a plurality of local data buses provided corresponding to said plurality of memory blocks each for transferring data with a corresponding memory block;
- a plurality of spare local data buses provided corresponding to said plurality of spare memory blocks each for transferring data with a corresponding spare memory block;
- a global data bus provided in common to said plurality of memory blocks and selectively coupled with a local data bus provided corresponding to a memory block including a selected normal memory cell;
- and
- a spare global data bus provided in common to said plurality of spare memory blocks and coupled simultaneously and selectively with a spare local data bus provided corresponding to k spare memory blocks including a spare memory block including a selected spare memory cell, said k being an integer no less than two.
4 more elements
A semiconductor memory device, comprising:
- a plurality of first memory blocks each having a plurality of normal memory cells arranged in a matrix of rows and columns;
- and
- a plurality of spare memory cells arranged in a matrix of rows and columns in a particular one of said plurality of first memory blocks,
- each row of said plurality of spare memory cells being capable of replacing a defective row including a defective normal memory cell in said plurality of first memory blocks.
1 more element
A semiconductor memory device, comprising:
- a plurality of first memory blocks each having a plurality of normal memory cells arranged in a matrix of rows and columns;
- a plurality of second memory blocks provided alternately with said plurality of first memory blocks along a column direction, of the memory blocks each having a plurality of normal memory cells arranged in a matrix of rows and columns;
- a plurality of third memory blocks each having a plurality of memory cells arranged in a matrix of rows and columns;
- a plurality of fourth memory blocks provided alternately with said third memory blocks in the column direction of the fourth memory blocks having a plurality of normal memory cells;
- a first spare array having a plurality of spare memory cells arranged in a matrix of rows and columns in a particular one of said plurality of first memory blocks, each row of those spare memory cells being capable of replacing a defective row including a defective memory cell in the third memory blocks;
- a second spare array having a plurality of spare memory cells arranged in a matrix of rows and columns in a particular one of said second memory blocks, each row of those spare memory cells being capable of replacing a defective row including a defective normal memory cell in said plurality of fourth memory blocks;
- a third spare array having a plurality of spare memory cells arranged in a matrix of rows and columns in a particular one of said third memory blocks, each row of those spare memory cells being capable of replacing a defective row including a defective memory cell in said plurality of first memory blocks;
- a fourth spare array having a plurality of spare memory cells arranged in a matrix of rows and columns in a particular one of said plurality of fourth memory block, each row of those spare memory cells being capable of replacing a defective row including a defective memory cell in said plurality of second memory blocks;
- and
- control circuitry for selectively driving one of the first to fourth memory blocks into a selected state in a normal operation mode, and selecting one of first and second memory blocks and one of the third and fourth memory blocks to drive selected memory blocks into a selected state in a particular operation mode.
7 more elements
A semiconductor memory device capable of operating in a normal mode for accessing data and in a refresh mode for holding data, comprising:
- a power source node for supplying a prescribed voltage;
- a plurality of memory blocks each having a plurality of memory cells arranged in a matrix of rows and columns and a repeating circuit group including a plurality of repeating circuits each having a common function for performing an operation related to a memory cell selection;
- a plurality of power source switch circuits provided corresponding to said plurality of memory blocks, each of the power source switch circuits for coupling said power source node and a repeating circuit group in a corresponding memory block, said plurality of power source switch circuits each causing a first current flow in a selected state and a second current flow smaller than said first current in a non-selected state;
- and
- control circuitry for selectively driving said plurality of power source switch circuits into a selected state according to an address signal such that the number of selected power source switch circuit(s) is different between said normal mode and said refresh mode.
2 more elements
Dependencies are inferred from the claim text.