Semiconductor memory device with redundant memory cells

A semiconductor memory device including a redundancy circuit, the redundancy circuit comprising:

• a fuse predecode signal bus including a plurality of predecode signal lines;
• a fuse predecode circuit connected to the fuse predecode signal bus for receiving a plurality of first address signals, the fuse predecode circuit including,
• a plurality of drivers each of which generates a drive signal in response to one of the first address signals,
• a plurality of terminal circuits connected to the predecode signal bus, the terminal circuits latching signals appeared on the predecode signal bus, and
• a plurality of fuse circuits each of which is connected between one of the predecode signal lines and a first potential source, each of the fuse circuits including a transistor having a control terminal connected to one of the drivers and a fuse connected to the transistor in series;
• a logic translate circuit connected to the fuse predecode signal bus, the logic translate circuit translating signals output from the fuse predecode circuit and outputting translated signals;
• a fuse decode circuit connected to the logic translate circuit, the fuse decode circuit decoding the translated signals and outputting a decode signal;
• and
• an address decode circuit connected to the fuse decode circuit, the address decode signal generating an address decode signal in response to a plurality of second address signals and the decode signal.

A redundancy circuit comprising:

• a plurality of predecode signal lines;
• a fuse predecode circuit connected to the fuse predecode signal lines for receiving a plurality of first address signals, the fuse predecode circuit including,
• a plurality of drivers each of which generates a drive signal in response to one of the first address signals,
• a plurality of terminal circuits connected to the predecode signal bus, the terminal circuits latching signals appeared on the predecode signal lines, and
• a plurality of fuse circuits each of which is connected between one of the predecode signal lines and a first potential source, each of the fuse circuits including a transistor having a control terminal connected to one of the drivers and a fuse connected to the transistor in series;
• a fuse decode circuit connected to the fuse predecode signal lines, the fuse decode circuit decoding signals appeared on the fuse predecode signal lines and outputting a decode signal;
• and
• an address decode circuit connected to the fuse decode circuit, the address decode signal generating an address decode signal in response to a plurality of second address signals and the decode signal.