System for setting memory voltage threshold
AssigneeFujitsu Limited
InventorShigekazu Yamada
Life of this patent
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AssigneeFujitsu Limited
InventorShigekazu Yamada
Estimating the term…
System to set threshold voltages in a memory device. The system includes apparatus to set voltage threshold levels of a plurality of memory cells in a memory device. The plurality of memory cells are coupled to a common word line. The apparatus includes a plurality of gates that are coupled between a voltage source and the plurality of memory cells, the gates include control inputs that receive control signals that open and close each gate, so that when a selected gate is closed, the voltge source is coupled to a selected memory cell and when the selected gate is open the current source is uncoupled from the selected memory cell. The apparatus also includes control logic that generates the control signals to open and close the gates to individually enable and disable programming of the voltage threshold of each of the memory cells.
Apparatus to set voltage threshold levels of a plurality of memory cells in a memory device, the plurality of memory cells are coupled to a common word line, the apparatus comprising:
A method for setting voltage threshold levels of a plurality of memory cells in a memory device, the plurality of memory cells are coupled to a common word line, the method comprising steps of:
Dependencies are inferred from the claim text.