Semiconductor memory device
AssigneeMatsushita Electric Industrial Co., Ltd.
InventorsMasashi Agata, Kazunari Takahashi
Life of this patent
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Abstract
The semiconductor memory device includes: a memory cell including a capacitor having a charge storage node and a first MIS transistor and a second MIS transistor each having a source connected to the charge storage node; a first word line and a first bit line respectively connected to the gate and the drain of the first MIS transistor; a second word line and a second bit line respectively connected to the gate and the drain of the second MIS transistor; and a timer circuit for generating a periodic signal having a predetermined period. The first word line or the second word line is activated in response to the periodic signal.
Claims9
A semiconductor memory device comprising:
- a memory cell including a capacitor having a charge storage node, and a first MIS transistor and a second MIS transistor each having a first source/drain terminal connected to the charge storage node;
- a first word line and a first bit line respectively connected to a gate and a second source/drain terminal of the first MIS transistor;
- a second word line and a second bit line respectively connected to a gate and a second source/drain terminal of the second MIS transistor;
- and
- a timer circuit for generating a periodic signal having a predetermined period,
- wherein the first word line or the second word line is activated in response to the periodic signal.
A semiconductor memory device comprising:
- a plurality of memory cells each including a capacitor having a charge storage node, and a first MIS transistor and a second MIS transistor each having a first source/drain terminal connected to the charge storage node;
- a plurality of first word lines and a plurality of first bit lines respectively connected to gates and second source/drain terminals of the first MIS transistors;
- a plurality of second word lines and a plurality of second bit lines respectively connected to gates and second source/drain terminals of the second MIS transistors;
- a timer circuit for generating a periodic signal having a predetermined period;
- an access word line selection circuit for selectively activating the plurality of first word lines in response to an external access request;
- and
- a refresh word line selection circuit for selectively activating the plurality of second word lines at the predetermined period with the periodic signal.
Dependencies are inferred from the claim text.