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US 2003/0169616 A1Published application
Ferroelectric memory wherein bit line capacitance can be maximized
AssigneeFujitsu Limited
InventorKouichi Noro
Life of this patent
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Abstract
In a ferroelectric memory, there are provided a plurality of word lines, a plurality of bit lines crossing there-with, a plurality of memory cells having ferroelectric capacitors arranged at the positions of these crossovers and a plurality of correction capacitors connectable with the bit lines. At least some of the plurality of correction capacitors are connected with a bit line so as to be capable of increasing bit line capacitance by a prescribed amount.
Claims13
A ferroelectric memory comprising:
- a plurality of word lines;
- a plurality of bit lines crossing said word lines;
- a plurality of memory cells, arranged at crossovers of said word lines and bit lines, including a ferroelectric capacitor;
- and
- a plurality of correction capacitors connectable with said bit lines,
- wherein at least a part of said plurality of correction capacitors are connected with said bit lines.
3 more elements
A ferroelectric memory comprising:
- a cell array region including a plurality of word lines, a plurality of bit lines crossing said word lines, and a plurality of memory cells which are arranged at crossovers of said word lines and bit lines and each include a ferroelectric capacitor and a transistor;
- and
- a plurality of correction capacitors connectable with said bit lines, and provided within said cell array region and/or provided at a periphery of said cell array region;
- wherein at least a part of said plurality of correction capacitors are connected with said bit lines.
1 more element
Dependencies are inferred from the claim text.