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US 2003/0169612 A1Published application
Static content addressable memory cell
AssigneeMicron Technology, Inc.
InventorShane Ching-Feng Hu
Life of this patent
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Abstract
A static content addressable memory (CAM) cell. The CAM cell includes a latch having complementary data nodes capacitively coupled to ground, first and second access transistors, each coupled between a data node of the latch and a respective data line. The gates of each access transistor is coupled to a word line such that when activated, the respective data node and data line are coupled. The CAM cell further includes a match circuit coupled to one of the complementary data nodes of the latch. The match circuit discharges a match line in response to a data value stored at the data node to which the match circuit is coupled and compare data present on the respective data line mismatching. Two of the CAM cells can be used to implement a full ternary CAM cell.
Claims42
In a content addressable memory (CAM) array having CAM cells arranged in rows of word lines and columns of data lines, a CAM cell, comprising:
- a bistable circuit coupled to a power supply and ground, the bistable circuit having first and second data nodes;
- first and second access transistors coupled to the first and second data nodes and first and second data lines, all respectively, for coupling the respective data node to the respective data line in response to activating a word line;
- first and second capacitors, each capacitor having a first terminal coupled to a respective data node and having a second terminal coupled to ground;
- and
- a match circuit having a search node coupled to the first data line, a cell node coupled to the first data node, and a match node coupled to a match line, the match circuit changing the logic state of the match line in response to search data provided on the first data line and the data stored at the first data node are mismatching.
2 more elements
In a content addressable memory (CAM) array having CAM cells arranged in rows of word lines and columns of data lines, a CAM cell, comprising:
- a first bistable circuit coupled to a power supply and ground, the first bistable circuit having first and second data nodes;
- a second bistable circuit coupled to the power supply and ground, the second bistable circuit having third and fourth data nodes;
- first and second access transistors coupled to the first and second data nodes and first and second data lines, all respectively, for coupling the respective data node to the respective data line in response to activating a word line;
- second and fourth access transistors coupled to the third and fourth data nodes and third and fourth data lines, all respectively, for coupling the respective data node to the respective data line in response to activating the word line;
- first, second, third, and fourth capacitors, each capacitor having a first terminal coupled to a respective data node and having a second terminal coupled to ground;
- and
- a match circuit having a first search node coupled to the first data line and a second search node coupled to the third data line, a first cell node coupled to the first data node and a second cell node coupled to the third data node, and a match node coupled to a match line, the match circuit changing the logic state of the match line in response to search data provided on the first data line and the first data node mismatch and search data provided on the third data line and the third data node mismatch.
4 more elements
A static content addressable memory array for a content addressable memory (CAM) device, comprising:
- a plurality of word lines;
- a plurality of data lines;
- a latch having complementary data nodes capacitively coupled to ground;
- first and second access transistors, each having a gate coupled to one of the plurality of word lines and coupled between a data node of the latch and a respective data line of the plurality;
- and
- a match circuit coupled to one of the complementary data nodes of the latch, the match circuit discharging a match line in response to a data value stored at the data node to which the match circuit is coupled and compare data present on the respective data line mismatching.
3 more elements
A content addressable memory (CAM) device, comprising:
- an address bus;
- a control bus;
- a data bus;
- an address decoder coupled to the address bus;
- a read/write circuit coupled to the data bus;
- and
- an array of CAM memory cells coupled to the address decoder, control circuit, and read/write circuit, the array comprising:
- a plurality of word lines;
- a plurality of data lines;
- a latch having complementary data nodes capacitively coupled to ground;
- first and second access transistors, each having a gate coupled to one of the plurality of word lines and coupled between a data node of the latch and a respective data line of the plurality;
- and
- a match circuit coupled to one of the complementary data nodes of the latch, the match circuit discharging a match line in response to a data value stored at the data node to which the match circuit is coupled and compare data present on the respective data line mismatching.
10 more elements
A content addressable memory (CAM) device, comprising:
- an address bus;
- a control bus;
- a data bus;
- an address decoder coupled to the address bus;
- a read/write circuit coupled to the data bus;
- and
- an array of CAM memory cells coupled to the address decoder, control circuit, and read/write circuit, each CAM cell comprising:
- a first bistable circuit coupled to a power supply and ground, the first bistable circuit having first and second data nodes;
- a second bistable circuit coupled to the power supply and ground, the second bistable circuit having third and fourth data nodes;
- first and second access transistors coupled to the first and second data nodes and first and second data lines, all respectively, for coupling the respective data node to the respective data line in response to activating a word line;
- second and fourth access transistors coupled to the third and fourth data nodes and third and fourth data lines, all respectively, for coupling the respective data node to the respective data line in response to activating the word line;
- first, second, third, and fourth capacitors, each capacitor having a first terminal coupled to a respective data node and having a second terminal coupled to ground;
- and
- a match circuit having a first search node coupled to the first data line and a second search node coupled to the third data line, a first cell node coupled to the first data node and a second cell node coupled to the third data node, and a match node coupled to a match line, the match circuit changing the logic state of the match line in response to search data provided on the first data line and the first data node mismatch and search data provided on the third data line and the third data node mismatch.
11 more elements
A computer system, comprising:
- a data input device;
- a data output device;
- a processor coupled to the data input and output devices;
- and
- a content addressable memory (CAM) device coupled to the processor, the CAM device comprising:
- an address bus;
- a control bus;
- a data bus;
- an address decoder coupled to the address bus;
- a read/write circuit coupled to the data bus;
- and
- an array of CAM memory cells coupled to the address decoder, control circuit, and read/write circuit, the array comprising:
- a plurality of word lines;
- a plurality of data lines;
- a latch having complementary data nodes capacitively coupled to ground;
- first and second access transistors, each having a gate coupled to one of the plurality of word lines and coupled between a data node of the latch and a respective data line of the plurality;
- and
- a match circuit coupled to one of the complementary data nodes of the latch, the match circuit discharging a match line in response to a data value stored at the data node to which the match circuit is coupled and compare data present on the respective data line mismatching.
15 more elements
A method for storing data in a content addressable memory, comprising:
- charging a first node of a first capacitor;
- activating a switch to couple a first node of a second capacitor to ground;
- maintaining a charge at the first node of the first capacitor.
A method of storing data in a content addressable memory, comprising:
- charging a first capacitor;
- shunting a second capacitor;
- and
- maintaining the charge on the first capacitor through a resistive current path.
1 more element
A method for storing data in a content addressable memory, comprising:
- charging a first capacitor;
- setting a bistable circuit to a first state;
- discharging a second capacitor in response to setting the bistable circuit;
- and
- maintaining the charge on the first capacitor.
2 more elements
Dependencies are inferred from the claim text.