Twin p-well CMOS imager
AssigneeMicron Technology, Inc.
InventorHoward F. Rhodes
Life of this patent
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Abstract
A CMOS imager which includes a substrate voltage pump to bias a doped area of a substrate to prevent leakage into the substrate from the transistors formed in the doped area. The invention also provides a CMOS imager where a photodetector sensor array is formed in a first p-well and readout logic is formed in a second p-well. The first p-well can be selectively doped to optimize cross-talk, collection efficiency and transistor leakage, thereby improving the quantum efficiency of the sensor array while the second p-well can be selectively doped and/or biased to improve the speed and drive of the readout circuitry.
Claims133
An imaging device comprising:
- a photosensitive area within a substrate for accumulating photo-generated charge in said area;
- a readout circuit comprising at least an output transistor formed in said substrate;
- and
- a substrate voltage pump coupled to a supply voltage and connected to supply said substrate with a voltage.
An imaging device comprising:
- a photosensitive device overlying a substrate for causing accumulation of the photo-generated charge in an underlying portion of said substrate;
- a readout circuit comprising at least an output transistor formed in said substrate;
- a reset transistor for resetting said node to a predetermined voltage;
- a row select transistor;
- and
- at least one substrate voltage pump coupled to a supply voltage and connected to supply said substrate with a voltage.
An imaging system for generating an output signal based on an image focused on the imaging system, the imaging system comprising:
- a plurality of pixel sensors arranged into an array of rows and columns, each pixel sensor being operable to generate a voltage at a diffusion node in a substrate corresponding to detected light intensity by the sensor;
- at least one substrate voltage pump coupled to a supply voltage and connected to supply said substrate with a voltage;
- a row select device to effectively operate said pixel sensors;
- a row decoder having a plurality of control lines connected to the sensor array, each control line being connected to the pixel sensors in a respective row, wherein the row decoder is operable to activate the pixel sensors in a row by said row select device;
- and
- a plurality of output circuits, each output circuit being connected to the respective pixel sensors in a column, each output circuit being operable to is store voltage signals received from a respective pixel sensor and to provide a pixel sensor output signal.
A system comprising:
- (i) a processor;
- and
- (ii) a CMOS imaging device coupled to said processor and including:
- a substrate;
- a photosensitive area within said substrate for accumulating photo-generated charge in said area;
- a readout circuit comprising at least an output transistor formed in said substrate;
- and
- a substrate voltage pump coupled to a supply voltage and connected to supply said substrate with a voltage.
A method for reducing the charge leakage across transistors formed in a substrate of a CMOS imager circuit, said method comprising negatively biasing said substrate with a substrate voltage pump, wherein said substrate voltage pump provides a voltage of from about −2.5 to about 2.5 volts to said substrate.
An imaging device comprising:
- a substrate;
- a photosensitive area within a first conductively doped well formed in said substrate for accumulating photo-generated charge in said area;
- and
- a readout circuit formed in a second conductively doped well.
An imaging device including a semiconductor integrated circuit substrate, said imaging device comprising:
- a photosensitive device formed in a first p-well in said substrate for accumulating photo-generated charge in an underlying portion of said substrate;
- a readout circuit formed in a second conductively doped well;
- a reset transistor formed in said first p-well in said substrate for resetting said node;
- and
- a row select transistor formed in said first p-well in said substrate.
86 The imaging device according to claim 84, wherein said photosensitive device is a photodiode.
88 The imaging device according to claim 84, further comprising:
- a controllable charge transfer region having a control terminal, said transfer region being formed in said first p-well in said substrate and adjacent said photosensitive area and having a node formed in a first doped area of said substrate connected to a gate of said output transistor;
- and
- at least one charge transfer device formed in said first p-well in said substrate for transferring charge from said photosensitive area to said node in accordance with a control signal applied to said control terminal.
An imaging system comprising:
- (i) a processor;
- and
- (ii) a CMOS imaging device coupled to said processor and including:
- a photosensitive area within a first p-well formed in a substrate for accumulating photo-generated charge in said area;
- and
- a readout circuit formed in a second conductively doped well.
Dependencies are inferred from the claim text.