Stalling pipelines in large designs

A stall-buffer for stalling modules in a computational pipeline, wherein the computational pipeline comprises a first module and a second module, wherein the first module and the second module are coupled together in order to propagate one or more signals from the first module to the second module, the stall-buffer comprising:

• an input operable to couple to an output of the first module;
• an output operable to couple to an input of the second module;
• a memory coupled to the input and the output for buffering signals;
• a stall-signal input for receiving a stall-signal, wherein the stall-signal is generated when the second module is not ready to receive the one or more signals from the first module;
• and
• wherein the stall-buffer is operable to buffer the one or more signals from the first module upon receiving the stall-signal.

A system for stalling modules in a computational pipeline, wherein the computational pipeline comprises a first module and a second module, comprising:

• a stall-signal operable to stall the first module when the second module is not ready to receive the one or more signals from the first module;
• and
• a stall-buffer operable to buffer the one or more signals from the first module upon receiving said stall-signal;
• wherein the first module and the second module are coupled together in order to propagate one or more signals from the first module to the second module.

A method for stalling modules in a computational pipeline, wherein the computational pipeline comprises a first module and a second module coupled together, comprising:

• asserting a stall-signal operable to stall the computational pipeline if the second module is not ready to receive one or more signals from the first module;
• propagating the one or more signals from the first module to the second module;
• buffering the one or more signals propagated from the first module in a stall-buffer in response to receiving the asserted stall-signal;
• buffering the stall-signal in the stall-buffer in response to receiving the asserted stall-signal;
• propagating the stall-signal to the first module in a next cycle after said buffering the stall-signal;
• and
• stalling the first module in response to the first module receiving the propagated stall-signal.

A method for stalling modules in a computational pipeline, wherein the computational pipeline comprises a first module and a second module coupled together, comprising:

• asserting a stall-signal operable to stall the computational pipeline if the second module is not ready to receive one or more signals from a first module, wherein the first module and the second module comprise a first stall-buffer and a second stall-buffer respectively;
• propagating the one or more signals from the first module to the second module;
• buffering the one or more signals propagated from the first module using a second stall-buffer in response to receiving the asserted stall-signal;
• buffering the stall-signal in the second stall-buffer in response to receiving the asserted stall-signal;
• propagating the stall-signal to the first module in a next cycle;
• stalling the first module in response to the first module receiving the propagated stall-signal.