Graphics data synchronization with multiple data paths in a graphics accelerator

The hardware accelerator wherein the convergence unit couples to the bus interface through a bus, wherein the host processor may read the synchronization register through the bus.

A graphics system comprising:

• a raster pipe configured to operate on geometry data to generate samples;
• a direct path configured operate on pixel data;
• a convergence unit configured to merge a first data stream including samples from the raster pipe and a second data stream including the pixel data from the direct path, and to forward the merged data stream to a frame buffer, wherein the convergence unit is further configured to identify an occurrence of a token in the merged data stream and to store the token in a synchronization register, wherein the synchronization register is readable by an external processor.