US 2003/0166321 A1 · Method of manufacturing semiconductor device

Abstract

The manufacturing method of the invention is applied to production of a semiconductor device including a memory area and a logic circuit area. The method first provides a semiconductor substrate, which has a conductive layer to make a word gate of the non-volatile memory device, a stopper layer formed above the conductive layer, and control gates formed as side walls on both side faces of the conductive layer via an ONO membrane, which are all located above a semiconductor layer in the memory area, as well as a gate electrode of an insulated gate field effect transistor formed above a semiconductor layer in the logic circuit area. The method subsequently forms an insulating layer over whole surface of the memory area and the logic circuit area on the semiconductor substrate, and carries out anisotropic etching of an upper portion in a part of the insulating layer. The method then polishes the insulating layer to make the stopper layer in the memory area exposed but not to make the gate electrode in the logic circuit area exposed. This arrangement makes the surface of the insulating layer sufficiently flat and even after the polishing process in the manufacturing method of the semiconductor device.

Claims4

Dependent claims

A method of manufacturing a semiconductor device, which comprises a memory area having a non-volatile memory device and a logic circuit area including a peripheral circuit of the non-volatile memory device, the manufacturing method comprising the steps of:

providing a semiconductor substrate, which has a conductive layer to make a word gate of the non-volatile memory device, a stopper layer formed above the conductive layer, and control gates formed as side walls on both side faces of the conductive layer via an ONO membrane, which are all located above a semiconductor layer in the memory area, as well as a gate electrode of an insulated gate field effect transistor formed above a semiconductor layer in the logic circuit area;
forming an insulating layer over whole surface of the memory area and the logic circuit area on the semiconductor substrate;
carrying out anisotropic etching of an upper portion in a part of the insulating layer;
and
polishing the insulating layer to make the stopper layer in the memory area exposed but not to make the gate electrode in the logic circuit area exposed.

2 more elements

forming a first insulating layer above a semiconductor layer;
forming a first conductive layer above the first insulating layer;
forming a stopper layer above the first conductive layer;
patterning the stopper layer and the first conductive layer in the memory area;
forming an ONO membrane over whole surface of the memory area and the logic circuit area;
forming a second conductive layer above the ONO membrane;
carrying out anisotropic etching of the second conductive layer, so as to form control gates as side walls via the ONO membrane on both side faces of the first conductive layer in at least the memory area;
etching out the stopper layer in the logic circuit area;
patterning the first conductive layer in the logic circuit area, so as to create a gate electrode of an insulated gate field effect transistor in the logic circuit area;
forming side wall insulating layers on both side faces of at least the gate electrode;
forming a first impurity layer as either one of a source area and a drain area of the non-volatile memory device and a second impurity layer as either one of a source area and a drain area of the insulated gate field effect transistor;
forming a silicide layer on surface of the first impurity layer, the second impurity layer, and the gate electrode;
forming a second insulating layer over whole surface of the memory area and the logic circuit area;
carrying out anisotropic etching of an upper portion in a part of the second insulating layer;
polishing the second insulating layer to make the stopper layer in the memory area exposed but not to make the gate electrode in the logic circuit area exposed;
etching out the stopper layer in the memory area;
and
patterning the first conductive layer in the memory area, so as to create a word gate of the non-volatile memory device in the memory area.

15 more elements

Dependencies are inferred from the claim text.

Method of manufacturing semiconductor device

Life of this patent

Method of manufacturing semiconductor device

Life of this patent

Abstract

Claims4