Method of fabricating poly spacer gate structure

A fabrication method of flash memory utilizing poly spacer as floating gate, comprising the steps of:

• providing a semiconductor substrate and depositing an oxide on a surface of said substrate;
• forming a predefined and patterned first dielectric on a surface of said oxide;
• depositing a first poly silicon on said substrate to cover said oxide and said first dielectric;
• depositing a second dielectric on a surface of said poly silicon;
• performing anisotropic etch to said second dielectric and forming dielectric spacer around projective sides of said first poly silicon;
• performing etch to said first poly silicon with said dielectric spacer as a mask to form poly spacer around said first dielectric, then removing said first dielectric;
• performing ion implantation to said substrate to form ion doped regions;
• depositing an insulating dielectric on said substrate to cover said poly spacer and said oxide;
• and
• forming a predefined second poly silicon on said insulating dielectric as a control gate.