Phase shifting circuit manufacture method and apparatus
AssigneeNumerical Technologies, Inc.
InventorsYao-Ting Wang, Yagyensh C. Pati
Life of this patent
Estimating the term…
Abstract
A method for manufacturing integrated circuits using opaque field, phase shift masking. One embodiment of the invention includes using a two mask process. The first mask is an opaque-field phase shift mask and the second mask is a single phase structure mask. A phase shift window is aligned with the opaque field using a phase shift overlap area on the opaque field. The phase shift mask primarily defines regions requiring phase shifting. The single phase structure mask primarily defines regions not requiring phase shifting. The single phase structure mask also prevents the erasure of the phase shifting regions and prevents the creation of undesirable artifact regions that would otherwise be created by the phase shift mask.
Claims12
A method for manufacturing at least a layer of material on an integrated circuit, comprising:
- exposing a semiconductor substrate treated with a material sensitive to radiation energy to said radiation energy using a first layout having phase shift areas in an opaque field to define a gate length dimension for a transistor having a diffusion region with a first width, the phase shift area having a width equal to the width of the diffusion region plus extension dimensions sufficient to tolerate mask misalignment errors, and
- exposing the semiconductor substrate treated with a material sensitive to radiation energy to said radiation energy using a second layout having opaque areas to define other structures.
A method for manufacturing at least a layer of material on an integrated circuit, comprising:
- exposing a semiconductor substrate treated with a material sensitive to radiation energy to said radiation energy using a phase shift layout having phase shift areas in an opaque field to define a structure;
- exposing the semiconductor substrate treated with a material sensitive to radiation energy to said radiation energy using a structure layout having opaque areas to define other structures, the opaque areas being spaced away by clear areas away from the phase shift areas by protection dimensions sufficient to tolerate mask misalignment errors.
A method for manufacturing at least a layer of material on an integrated circuit, comprising:
- exposing a semiconductor substrate treated with a material sensitive to radiation energy to said radiation energy using a phase shift layout having phase shift areas in an opaque field to define a structure;
- exposing the semiconductor substrate treated with a material sensitive to radiation energy to said radiation energy using a structure layout having opaque areas to define other structures and protect areas to protect the structure from exposure, the protect area having a width equal to the width of the diffusion region plus protection dimensions sufficient to tolerate mask misalignment errors.
A method for manufacturing at least a layer of material on an integrated circuit, comprising:
- exposing a semiconductor substrate treated with a material sensitive to radiation energy to said radiation energy using a phase shift layout having phase shift areas in an opaque field to shrink a gate length dimension for a transistor to a smaller dimension, wherein the phase shift areas include a θ degree phase shift area, and an adjacent (180+θ) phase shift area, and a chrome strip between the θ degree phase shift area, and the adjacent(180+θ), the chrome strip having a width affecting the smaller dimension of the gate length;
- exposing the semiconductor substrate treated with a material sensitive to radiation energy to said radiation energy using a structure layout having opaque areas to define other structures.
A method for manufacturing at least a layer of material on an integrated circuit, comprising:
- exposing a semiconductor substrate treated with a material sensitive to radiation energy to said radiation energy using a first layout having first and second clear areas in an opaque field, the first and second clear areas separated by an opaque line to affect a gate length dimension for a transistor having a diffusion region with a first width, the first and second clear areas having a width equal to the width of the diffusion region plus extension dimensions sufficient to tolerate mask misalignment errors, and
- exposing the semiconductor substrate treated with a material sensitive to radiation energy to said radiation energy using a second layout having opaque areas to define other structures.
A process for manufacturing at least a layer of material of an integrated circuit, said processing comprising:
- a phase shift exposure step in which a photoresist coated substrate is exposed to light using a phase shift mask, said phase shift mask comprising adjacent first clear areas that transmit light out of phase with each other to form a gate dark area on the photoresist coated substrate using destructive light interference, said gate dark area having a larger dimension and a smaller dimension, said smaller dimension being equal to the length of a gate of a transistor to be formed on said layer, said larger dimension being equal to the width of a diffusion region of said transistor plus extension dimensions, said extension dimension being a function of a maximum possible mask misalignment;
- and
- a structure exposure step in which the photoresist coated substrate is exposed to light using a structure mask, said structure mask comprising opaque areas, wherein said opaque areas define a protection area to prevent exposure of said gate.
Dependencies are inferred from the claim text.