Jitter-detecting circuit, receiving circuit including the jitter-detecting circuit, and communication system

A jitter-detecting circuit for detecting jitter from a binary-equalizing-data signal including a synchronization clock comprising:

• a delay circuit for delaying the phase of the clock by a predetermined value;
• a flip-flop for sampling the clock delayed by the delay circuit at the leading edge or trailing edge of the binary-equalizing-data signal;
• and
• an average-value-detecting circuit for detecting and outputting the average value of outputs of the flip-flop.

A receiving circuit comprising:

• a light receiving element for converting an optical signal into an electrical signal;
• a bias circuit for supplying a predetermined bias voltage to the light receiving element;
• a preamplifier for amplifying the electrical signal supplied from the light receiving element;
• a limiter amplifier for binary-identifying the electrical signal supplied from the preamplifier by using an identification voltage;
• a jitter-detecting circuit for detecting jitter by using an output of the limiter amplifier and a synchronization clock extracted from the output;
• and
• a control circuit for controlling the identification voltage so that an output of the jitter-detecting circuit is minimized.