Deserializer

A method for deserializing a stream of consecutive data bits, comprising:

• sampling each of the consecutive data bits at times defined by a first plurality of clock phases generated by a single receiver clock so as to generate initial data values of each of the consecutive data bits;
• grouping the initial data values into a second plurality of sampling phase sets, according to the clock phases at which the values were sampled;
• assigning each of the sampling phase sets a respective grade responsive to at least some of the initial data values;
• selecting a decoding phase set from the sampling phase sets responsive to the respective grades;
• and
• decoding the stream responsive to the initial data values of the decoding phase set to generate decoded values of the consecutive bits.

A receiver for deserializing data conveyed on a first plurality of channels, comprising:

• a single clock which is adapted to generate a second plurality of clock phases;
• and
• a first plurality of deserializers, respectively coupled to the first plurality of channels so as to receive a respective data stream as consecutive data bits, each deserializer comprising:
• a sample generator which is adapted to sample the respective data stream so as to generate initial data values of each of the consecutive data bits at times defined by the second plurality of clock phases;
• and
• digital circuitry which is adapted to:
• group the initial data values into a third plurality of sampling phase sets, according to the clock phases at which the values were sampled,
• assign each of the sampling phase sets a respective grade responsive to at least some of the initial data values,
• select a decoding phase set from the sampling phase sets responsive to the respective grades, and
• decode the respective data stream responsive to the initial data values of the decoding phase set to generate decoded values of the consecutive bits.

A method for deserializing data conveyed on a first plurality of channels, comprising:

• generating a second plurality of clock phases from a single clock;
• conveying the second plurality of clock phases to a first plurality of deserializers;
• and
• coupling the first plurality of deserializers to the first plurality of channels so as to receive therefrom a respective data stream as consecutive data bits, each deserializer comprising:
• a sample generator which is adapted to sample the respective data stream so as to generate initial data values of each of the consecutive data bits at times defined by the second plurality of clock phases, and
• digital circuitry which is adapted to:
• group the initial data values into a third plurality of sampling phase sets, according to the clock phases at which the values were sampled,
• assign each of the sampling phase sets a respective grade responsive to at least some of the initial data values,
• select a decoding phase set from the sampling phase sets responsive to the respective grades, and
• decode the respective data stream responsive to the initial data values of the decoding phase set to generate decoded values of the consecutive bits.