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US 2003/0165077 A1Published application
Semiconductor memory device permitting early detection of defective test data
AssigneeMitsubishi Denki Kabushiki Kaisha
InventorYutaka Ikeda
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Abstract
In a test mode, read data is output from a memory array with each of N latch circuits in an output circuit being set to an operating state under the control of a latency setting circuit. Thus, the data transmission period can be set shorter in the test mode than in a normal data reading operation, and a time required for testing the read data in the test mode is shortened.
Claims6
A semiconductor memory device, comprising:
- a memory array storing data;
- a data output circuit transmitting read data output from said memory array to a data output node;
- and
- a latency setting circuit adjusting a data transmission period from a time when a data reading operation is designated to a time when said read data is transmitted to said data output node by controlling an operation timing of said data output circuit,
- said latency setting circuit setting said data transmission period shorter in a test mode than in a normal data reading operation.
2 more elements
Dependencies are inferred from the claim text.