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AssigneeSTMicroelectronics S.r.l.
InventorsFederico Pio, Enrico Gomiero, Paola Zuliani
Estimating the term…
The invention relates to a method of adjusting the erase/program voltage in semiconductor non-volatile memories. The memories are formed of at least one matrix of memory cells having a floating gate, a control gate, and drain and source terminals, and are organized by the byte in rows and columns, each byte comprising a group of cells having respective control gates connected in parallel with one another to a common control line through a selection element of the byte switch type, and each cell being connected to a respective control column through a selection element of the bit switch type. Advantageously, a double adjustment is provided for the program voltage of the memory cells, whereby the program voltage during the erasing phase can be higher in modulo than the program voltage during the writing phase. This is achieved by providing respective adjusters connected between a program voltage generator and the cell matrix, or alternatively forming the bit switch element inside a well and the byte switch element directly in the substrate.
A method of adjusting a program voltage in semiconductor non-volatile memories comprising at least one matrix of memory cells having a floating gate, a control gate, and drain and source terminals, and are organized by the byte in rows and columns, each byte having a group of cells having respective control gates connected in parallel with one another to a common control line through a byte switch selection element, and each cell being connected to a respective control column through a bit switch selection element, the method comprising:
A process for fabricating a non-volatile memory device integrated in a semiconductor comprising:
A memory structure comprising:
A memory cell structure in a semiconductor substrate of a first type, the structure comprising:
Dependencies are inferred from the claim text.