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US 2003/0165073 A1Published application
Content addressable memory (CAM) devices having reliable column redundancy characteristics and methods of operating same
AssigneeIntegrated Device Technology, Inc.
InventorsChuen-Der Lien, Chau-Chin Wu
Life of this patent
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Abstract
Content addressable memory (CAM) devices provide improved reliability by inhibiting disabled CAM cells within defective (or unused redundant columns) from contributing to either sustained or intermittent look-up errors when the CAM device is operated in an intended application. The improved reliability may be achieved in volatile CAM devices by configuring (e.g., programming) each column driver that is associated with a CAM array having a defective column therein to preserve intentionally written data and/or mask values of the disabled CAM cells across repeated power reset events.
Claims52
A content addressable memory (CAM) device, comprising:
- a CAM array having a plurality of columns of CAM cells therein;
- and
- a bit line control circuit that drives at least one disabled CAM cell in a disabled one of the plurality of columns of CAM cells with a respective fixed data value whenever the at least one disabled CAM cell undergoes a write operation.
A content addressable memory (CAM) device, comprising:
- a CAM array having a plurality of main columns of CAM cells and at least one redundant column of CAM cells therein;
- and
- a bit line control circuit that is programmed to preserve data values of column disabled CAM cells across a power reset event so that each column disabled CAM cell associated with a row containing a valid entry prior to the power reset event is rewritten again with a same data value it had prior to the power reset event as its respective row is updated with a valid entry following the power reset event.
A content addressable memory (CAM) device, comprising:
- a CAM array having a disabled column of volatile CAM cells therein;
- and
- a bit line control circuit that is electrically coupled to said CAM array and is programmed to preserve data and/or mask values of disabled volatile CAM cells in the disabled column across repeated power reset events.
A content addressable memory (CAM) device, comprising:
- a CAM array having a plurality of main columns of CAM cells and at least one redundant column of CAM cells therein;
- and
- a bit line control circuit that is fuse-programmed to drive at least one CAM cell in a defective one of said plurality of main columns of CAM cells with a respective fixed data value whenever the at least one CAM cell undergoes a write operation and to mask the defective one of said plurality of main columns of CAM cells whenever said CAM array undergoes a search operation.
A content addressable memory (CAM) device, comprising:
- a CAM array having a plurality of columns of CAM cells therein;
- and
- a bit line control circuit that is programmed to drive a disabled column of CAM cells with a same data value whenever a row of said CAM array is written to.
A content addressable memory (CAM) device, comprising:
- a CAM array having a plurality of main columns of CAM cells and at least one redundant column of CAM cells therein;
- and
- a bit line control circuit that is fuse-programmed to drive each CAM cell in a unused redundant column of CAM cells with a respective fixed data value whenever the respective CAM cell is written to.
A content addressable memory (CAM) device, comprising:
- a CAM array having an inactive redundant column of volatile CAM cells therein;
- and
- a bit line control circuit that is electrically coupled to said CAM array and is programmed to preserve intentionally written data and/or mask values of the volatile CAM cells in the inactive redundant column across repeated power reset events.
A content addressable memory (CAM) device, comprising:
- a CAM array having a plurality of main columns of CAM cells and at least one redundant column of CAM cells therein;
- and
- control circuitry that is fuse-programmed to write a plurality of disabled CAM cells within a defective one of said plurality of main columns of CAM cells with a same fixed data value so that each of the plurality of disabled CAM cells can be reliably masked whenever said CAM array is searched.
A content addressable memory (CAM) device, comprising:
- a CAM array having a plurality of main columns of CAM cells and at least one redundant column of CAM cells therein;
- and
- a bit line control circuit electrically coupled by bit and/or data lines to said CAM array, said bit line control circuit comprising one or more programmable circuit elements therein that cause said bit line control circuit to recognize the at least one redundant column of CAM cells as a replacement for one of said plurality of main columns of CAM cells and, upon recognition, to drive each of a first plurality of CAM cells in a defective one of said plurality of main columns of CAM cells with a same fixed data value each and every time a CAM cell in the first plurality undergoes a write operation.
A content addressable memory (CAM) device, comprising:
- a CAM array;
- and
- a bit/data line control circuit that is programmed to replace a defective column of CAM cells in said CAM array with another column of CAM cells in said CAM array and, upon replacement, to drive the defective column of CAM cells with fixed write data during write operations so that, consistent with post-manufacture yield testing, CAM cells within the defective column are precluded from contributing to either sustained or intermittent look-up errors caused when one or more defective transistors within the defective column of CAM cells prevent successful masking of the defective column during an operation to compare valid entries in said CAM array with a search word applied to said programmable bit/data line control circuit.
A method of operating a content addressable memory (CAM) device having a CAM array therein and a bit/data line control circuit electrically coupled to normal and redundant columns of CAM cells in the CAM array, said method comprising the step of:
- programming the bit/data line control circuit to drive a respective fixed data value into at least a first plurality of disabled cells within a defective normal column of CAM cells when rows containing these first plurality of disabled cells are written with valid entries, so that at commencement of each search operation occurring while the CAM array is at least partially full of the valid entries, each and every one of the first plurality of disabled cells being masked retains its respective fixed data value.
A method of operating a content addressable memory (CAM) device having a CAM array therein and a column control circuit electrically coupled to the CAM array, said method comprising the steps of:
- programming the column control circuit to:
- (i) activate a redundant column of CAM cells within the CAM array, (ii) disable a defective column of CAM cells within the CAM array, and (iii) preserve data and/or mask values of volatile CAM cells in the defective column across repeated power reset events.
A content addressable memory (CAM) device, comprising:
- a CAM array;
- and
- a column control circuit that is programmed to reboot an unused redundant column of volatile CAM cells within said CAM array upon power-up in a manner that preserves the data values written into each of the volatile CAM cells within the unused redundant column prior to the power-up.
A content addressable memory (CAM) device, comprising:
- a CAM array having a plurality of main columns of CAM cells and a disabled redundant column of CAM cells therein;
- and
- a bit line control circuit that is programmed to preserve data values of redundant CAM cells in the redundant column across a power reset event so that each disabled redundant CAM cell residing in a row containing a valid entry prior to the power reset event is rewritten again with a same data value it had prior to the power reset event as its respective row is updated with a new valid entry following the power reset event.
A content addressable memory (CAM) device, comprising:
- a CAM array;
- and
- control circuitry that is programmed to reboot a disabled column of volatile CAM cells within said CAM array upon power-up in a manner that preserves the data values written into each of the volatile CAM cells within the disabled column prior to the power-up.
A content addressable memory (CAM) device, comprising:
- a CAM array having a disabled column of CAM cells therein;
- and
- control circuitry that writes a first data value into a first CAM cell in the disabled column each and every time a row containing the first CAM cell is written with an entry.
A content addressable memory (CAM) device, comprising:
- an array of CAM cells arranged as a plurality of rows of CAM cells and a plurality of columns of CAM cells, with at least a first CAM cell in said array comprising a first data RAM cell and a second data/mask RAM cell that share a respective word line and are separated by respective compare logic.
A method of operating a content addressable memory (CAM) device, comprising the steps of:
- loading a first data value and second data/mask value into a CAM cell comprising first and second RAM cells that share a respective word line and are separated by compare logic that is electrically connected to an output of the first RAM cell and an output of the second RAM cell;
- precharging a match line and a pseudo-ground line that are electrically coupled to the compare logic;
- enabling an equalization transistor having a first current carrying terminal electrically coupled to a true input of the compare logic and a second current carrying terminal electrically coupled to a differential input of the compare logic, to thereby transfer charge between a true data line that is electrically coupled to an input of the first RAM cell and a complementary data line that is electrically coupled to an input of the second RAM cell for a duration sufficient to substantially equilibrate a potential of the true data line with a potential of the complementary data line;
- then
- driving the true and complementary data lines with a respective bit of a comparand while the equalization transistor is disabled;
- and then
- comparing a state of the CAM cell with the bit of the comparand to detect a match therebetween, in response to pulling the pseudo-ground line low from a precharged level.
4 more elements
A content addressable memory (CAM) device, comprising:
- a CAM array having a plurality of disabled CAM cells therein that span a disabled column, with each of the disabled CAM cells in the plurality comprising a first data RAM cell and a second data/mask RAM cell that share a respective word line and are separated by respective compare logic;
- and
- control circuitry that writes a first data value into a first disabled CAM cell in the disabled column whenever a row containing the first disabled CAM cell is written with a new entry.
A method of operating a content addressable memory (CAM) device, comprising the steps of:
- writing a first data value and second data/mask value into a CAM cell comprising first and second RAM cells that share a respective word line and are separated by compare logic having true and complementary data inputs that are electrically coupled to true and complementary data lines, respectively;
- precharging a match line and a pseudo-ground line that are electrically coupled to the compare logic;
- at least partially equilibrating a potential of the true data line with a potential of the complementary data line by transferring charge therebetween and then driving the true and complementary data lines rail-to-rail with a bit of a comparand;
- and then
- comparing a state of the CAM cell with the bit of the comparand to detect a match therebetween, in response to pulling the precharged pseudo-ground line low.
2 more elements
A content addressable memory (CAM) device, comprising:
- a CAM array having a plurality of columns of CAM cells therein;
- a bit line control circuit that is programmed to drive a disabled column of CAM cells with a same data value whenever a CAM cell in the disabled column is written to;
- and
- an equalization transistor electrically coupled across a pair of differential data lines associated with the disabled column.
1 more element
A method of operating a content addressable memory (CAM) device, comprising the steps of:
- writing a first data value and first data/mask value into a disabled column CAM cell having first and second RAM cells therein that share a first word line by simultaneously driving a first pair of bit lines connected to the first RAM cell with opposite rail voltages and a second pair of bit lines connected to the second RAM cell with opposite rail voltages, while the first word line is active;
- writing a second data value and second data/mask value into an active column CAM cell having third and fourth RAM cells therein that share the first word line by simultaneously driving a third pair of bit lines connected to the third RAM cell with opposite rail voltages and a fourth pair of bit lines connected to the fourth RAM cell with opposite rail voltages, while the first word line is active;
- precharging a match line that is electrically coupled to the disabled column CAM cell and the active column CAM cell;
- at least partially equilibrating a potential of a true data line that is electrically coupled to the active column CAM cell with a potential of a complementary data line that is electrically coupled to the active column CAM cell by transferring charge therebetween and then driving the true and complementary data lines with opposite rail-to-rail voltages that represent a respective bit of a comparand;
- and then
- comparing the bit of the comparand with the second data value and second data/mask value stored in the active column CAM cell while simultaneously masking the disabled column CAM cell.
3 more elements
A method of operating a content addressable memory (CAM) device, comprising the step of:
- rebooting a disabled column of volatile CAM cells within a CAM array in response to a power reset event by writing entries into the CAM array in a manner that preserves identical data and/or mask values written into each of the volatile CAM cells within the disabled column prior to the power reset event.
A content addressable memory (CAM) device, comprising:
- a CAM array having a disabled CAM cell therein that comprises a first RAM cell and a second RAM cell that share a respective word line;
- a first pair of differential bit lines electrically connected to the first RAM cell and a second pair of differential bit lines electrically connected to the second RAM cell;
- and
- a bit/data line control circuit that is fuse-programmed to clamp a first one of the first pair of differential bit lines and a first one of the second pair of differential bit lines at a first voltage level when said CAM array undergoes reading, writing and search operations.
1 more element
Dependencies are inferred from the claim text.