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US 2003/0164830 A1Published application
Yield enhancement of complex chips
Assignee3Dlabs Inc., Ltd.
InventorOsman Kent
Life of this patent
Estimating the term…
Abstract
A graphics processing chip which includes parallel texturing pipelines, with task allocation units which can bypass inoperative ones of said pipelines. Chips which have some but not all pipelines operative can still have full functionality, although performance is reduced.
Claims7
A graphics processor, comprising:
- a plurality of parallellized graphics computational units;
- and
- one or more task allocation units programmed to bypass defective ones of said subunits within said groups, and to distribute incoming tasks only among operative ones of said subunits.
An integrated circuit, comprising:
- a plurality of parallellized groups of identical processing subunits;
- task allocation units associated with ones of said groups;
- wherein said task allocation units are programmed to bypass defective ones of said subunits within said groups, and to distribute incoming tasks only among operative ones of said subunits;
- whereby defects which disable some but not all of said subunits in any one group are not necessarily fatal.
1 more element
Dependencies are inferred from the claim text.