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US 2003/0164823 A1Published application
3D graphics accelerator architecture
Assignee3Dlabs Inc., Ltd.
InventorsDavid Robert Baldwin, Nicholas J.N. Murphy
Life of this patent
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Abstract
A graphics accelerator with a byte-tiled memory architecture, and a high-speed image download path which provides higher bandwidth than the message-passing pipeline.
Claims4
A graphics accelerator, comprising:
- a plurality of specialized processing subunits, interconnected through a serial message-passing interface to provide a generally pipelined graphics accelerator architecture;
- and
- a memory interface which provides a high bandwidth interface directly to a local buffer associated with said graphics accelerator.
A graphics accelerator, comprising:
- a plurality of specialized processing subunits, interconnected through a serial message-passing interface to provide a reconfigurably pipelined graphics accelerator architecture;
- at least one of said specialized processing subunits comprising multiple subprocessors connected to operate in parallel on separate tasks;
- and
- a high bandwidth memory interface which interfaces to a local buffer of said graphics accelerator;
- wherein said serial interface also permits downloading of image data to ones of said subunits.
2 more elements
Dependencies are inferred from the claim text.