High frequency loss of signal detector
AssigneeBroadcom Corporation
InventorsAfshin Momtaz, Pang-Cheng Hsu
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Abstract
Methods and circuitry for implementing high speed loss-of-signal detectors for use in Gb/s telecommunication applications. The invention measures bit error rate (BER) of the incoming data by comparing the phase of the clock signal extracted from the incoming data with that of a delayed version of the incoming data. The results of this comparison are averaged over time to arrive at the BER. The measured BER is compared to a predetermined threshold value to detect a loss-of-signal condition. The invention adjusts the amount of delay of the incoming data in such a manner as to minimize the capacitive loading on the data line and clock line introduced by the loss-of-signal circuitry.
Claims21
In a receiver that includes a clock recovery circuit for extracting a recovered clock signal from an incoming data signal, a loss-of-signal detector comprising:
- a delay circuit coupled to receive the incoming data signal and configured to shift a phase of the incoming data signal by a predetermined delay AT to generate a delayed data signal;
- a flip-flop coupled to receive the recovered clock signal at one input and the delayed data signal at a clock input;
- an integrator coupled to an output of the flip-flop;
- a switch coupled to the integrator and configured to reset the integrator;
- and
- a comparator having a first input coupled to an output of the integrator and a second input coupled to a threshold voltage,
- wherein, the delay circuit is configured to shift the phase of the incoming data signal in a manner that is symmetrical with respect to a sampling edge of the clock signal.
The loss-of-signal detector of claim 2 wherein the flip-flop is configured to generate an error signal when a transition of the delayed data signal falls outside of the range (T/2)±ΔT, where T is the period of the recovered clock signal.
A high speed receiver comprising:
- a clock and data recovery block coupled to receive an incoming data signal and configured to extract a recovered clock signal from the incoming data signal;
- a retiming circuit coupled to receive the incoming data and the recovered clock signal and configured to generate a retimed data signal for further processing;
- and
- a statistical loss-of-signal (SLOS) detector coupled to receive the recovered clock signal and the incoming data signal, and configured to measure a bit error rate of the incoming data signal and to detect a loss-of-signal condition,
- wherein the SLOS detector is configured such that it adds as capacitive loading a single flip-flop to the recovered clock signal and a single delay circuit to the incoming data signal.
In a receiver that includes a clock recovery circuit for extracting a recovered clock signal from an incoming data signal, a method for detecting statistical loss of signal, the method comprising:
- delaying the incoming data signal by a window ΔT that is symmetrical relative to the recovered clock signal;
- latching the recovered clock signal using the delayed data signal as clock to generate an error signal, wherein a single latch generates the error signal whenever a transition of the delayed data signal falls outside of the range (T/2)±ΔT, where T is the period of the recovered clock signal;
- integrating a plurality of error signals over a predetermined period of time τint to arrive at a bit error rate of the incoming data signal;
- and
- comparing the bit error rate with a predetermined threshold to detect a loss-of-signal condition.
Dependencies are inferred from the claim text.