US 2003/0164723 A1 · Output buffer circuit

Abstract

There is provided an output buffer circuit which can realize high speed voltage transition of an output signal while generation of noise due to signal transition is suppressed. On the occasion of driving a PMOS transistor P1, in the period of the state I, when the NMOS transistor N11 and NMOS transistors N12, N13 are turned ON, voltage of the output stage PMOS gate terminal AP1 is sharply dropped and the PMOS transistor P1 is turned ON. While the signal is propagated in the shortest delay time to the circuit of next stage, when the NMOS transistor N11 and NMOS transistor N12 are turned ON in the state II, disturbance of signal waveform can be suppressed by limiting a through-rate of the voltage drop of the output stage PMOS gate terminal AP1. Driving capability of the PMOS transistor P1 can be variably controlled by controlling the bias condition of a control signal AP1 by switching, for every state, the NMOS transistors N12 to N14 which are turned ON.

Claims12

Dependent claims

An output buffer circuit comprising:

an output section for driving an output terminal which outputs a binary signal to the predetermined voltages;
and
a bias control section for variably controlling driving capability of the output section by variably controlling a bias to drive the output section in the transition period where the output terminal reaches the predetermined voltages.

An output buffer circuit comprising:

a first output section for driving an output terminal to output a binary signal to the first predetermined voltage;
a second output section for driving the output terminal to the second predetermined voltage;
a first bias control section for variably controlling driving capability of the first output section by variably controlling a first bias to drive the first output section in the transition period in which the output terminal reaches the first predetermined voltage;
a second bias control section for variably controlling driving capability of the second output section by variably controlling a second bias to drive the second output section in the transition period in which the output terminal reaches the second predetermined voltage;
a first non-drive control section which is driven simultaneously with the first bias control section for not driving the second output section by controlling the second bias before the first output section is driven;
and
a second non-drive control section which is driven simultaneously with the second bias control section for not driving the first output section by controlling the first bias before the second output section is driven.

4 more elements

Dependencies are inferred from the claim text.

Output buffer circuit

Life of this patent

Output buffer circuit

Life of this patent

Abstract

Claims12