System and method for compensating for the effects of process, voltage, and temperature variations in a circuit

A circuit comprising:

• one or more inverters, each having an input port, an output port, and being configured to (i) receive a respective one of one or more input signals, (ii) delay the respective input signal, and (iii) provide the delayed signal to the inverter output port;
• one or more logic devices, each corresponding to one of the inverters and including at least two input ports and an output port, wherein a first of the at least two input ports is configured to receive the inverted signal from its corresponding inverter;
• and
• one or more charge storing devices, each corresponding to one of the logic devices and having a first end coupled, at least indirectly, to a second of the corresponding at least two input ports and a second end coupled to a common node of its corresponding logic device, each charge storing device being configured to (i) receive the respective input signal and (ii) sense a rate of change in voltage of the respective input signal, the sensed voltage being representative of a corresponding current;
• wherein the output port of each logic device is configured to produce an output signal responsive to the delayed input signal received from its corresponding inverter and the corresponding current of its corresponding charge device.

A circuit comprising:

• a first stage including first and second active devices, each including three nodes, a junction formed of first nodes of the first and second devices forming a first circuit input port configured to receive an input signal, a junction formed of respective second and third nodes of the first and second devices forming a first stage output port configured to output a delayed signal;
• a second stage including (i) third, fourth, fifth, and seventh active devices, a junction formed of first nodes of the third and fourth active devices forming a first second stage input port, the first second stage input port being coupled to the first stage output port and (ii) an output port formed of a junction of a respective one of second and third nodes of the third and sixth active devices and the other of the second and third node of the fourth active device, the output port being configured to output an output drive signal;
• and
• a charge storing device configured to sense a rate of change of predetermined characteristics of the input signal, the charge storing device having a first end forming a second circuit input port and a second end coupled to a first node of the fifth and sixth devices, the other of the second and third node of the fifth device being coupled to an open node of the fourth device;
• wherein the second circuit input port is configured to receive the input signal;
• and
• wherein the first output drive signal is responsive to the delayed signal and the sensed rate of change.

A circuit comprising:

• a first portion including:
• a first inverter including first and second active devices, each including first, second, and third nodes, a junction formed of the first nodes of the first and second devices forming a first inverter input port configured to receive a first input signal, a junction formed of the respective second and third nodes of the first and second devices forming a first inverter output port configured to output a first delayed signal;
• a NAND gate including (i) third, fourth, fifth, and sixth active devices, a junction formed of first nodes of the third and fourth active devices forming a NAND gate input port, the NAND gate input port being coupled to the first inverter output port and (ii) a NAND gate output port formed of a junction of second nodes of the third and sixth active devices and a third node of the fourth active device, the NAND gate output port being configured to output a first output drive signal;
• and
• a first charge storing device configured to sense a rate of change of predetermined characteristics of the first input signal, the charge storing device having a first end forming a second first portion input port and a second end coupled to a first node of the fifth and sixth devices, a third node of the fifth device being coupled to a second node of the fourth device;
• wherein the first portion input port is configured to receive the first input signal;
• and
• wherein the first output drive signal is responsive to the first delayed signal and the sensed rate of change of the first input signal;
• and
• a second portion including:
• a second inverter including first and second active devices, each including first, second, and third nodes, a junction formed of the first nodes of the first and second devices forming a second inverter input port configured to receive a second input signal, a junction formed of the respective second and third nodes of the first and second devices forming a second inverter output port configured to output a second delayed signal;
• a NOR gate including (i) third, fourth, fifth, and sixth active devices, a junction formed of first nodes of the third and fourth active devices forming a NOR gate input port, the NOR gate input port being coupled to the second inverter output port and (ii) a NOR gate output port formed of a junction of third nodes of the third and sixth active devices and a second node of the fourth active device, the NOR gate output port being configured to output a second output drive signal;
• and
• a second charge storing device configured to sense a rate of change of predetermined characteristics of the second input signal, the second charge storing device having a first end forming a second portion input port and a second end coupled to a first node of the fifth and sixth devices, a second node of the fifth device being coupled to a third node of the fourth device;
• wherein the second portion input port is configured to receive the second input signal;
• and
• wherein the second output drive signal is responsive to the second delayed signal and the sensed rate of change of the second input signal.

A circuit comprising:

• first and second active devices, a junction formed of first nodes of the first and second devices forming a first input port and a junction formed of respective second and third nodes of the first and second devices forming a first output port;
• third, fourth, and fifth active devices, a gate of the third device being coupled to the first output port, a source of the third device being connected to a drain of the fourth device, and a drain of the third device being connected to a source of the fifth device, the drain of the third device and the source of the fifth device forming an output port;
• wherein a gate of the fifth device forms a second input port;
• sixth, seventh, and eighth active devices, a gate of the sixth device being connected to a gate of the fourth device, a drain of the sixth device being connected to a source of the seventh device, the gate and drain of the sixth device being connected together;
• wherein a gate of the seventh device is connected to a gate of the eight device, the gate and a source of the eighth device being connected together;
• and
• a charge storing device having a first end forming a third input port and a second end connected to the source of the eighth device.

A circuit comprising:

• first and second active devices, a junction formed of first nodes of the first and second devices forming a first input port and a junction formed of respective second and third nodes of the first and second devices forming a first output port;
• third, fourth, and fifth active devices, a gate of the third device being coupled to the first output port, a source of the third device being connected to a drain of the fourth device, and a drain of the third device being connected to a source of the fifth device, the source of the third device and the drain of the fourth device forming an output port;
• wherein a gate of the fourth device forms a second input port;
• sixth, seventh, and eighth active devices, a gate of the sixth device being connected to a gate of the fourth device, a drain of the sixth device being connected to a source of the seventh device, the gate and drain of the sixth device being connected together;
• wherein a gate of the seventh device is connected to a gate of the eight device, the gate and a source of the eighth device being connected together;
• and
• a charge storing device having a first end forming a third input port and a second end connected to the source of the eighth device.

A method of compensating for voltage variations in a gate signal received as an input to an adjusting circuit, the adjusting circuit including an inverter, a logic gate, and a charge storing device, the method comprising:

• receiving the gate signal as an input to the inverter, the inverter delaying the received gate input signal and producing a first output signal;
• receiving the gate signal as an input to the charge storing device, the charge storing changing current characteristics of the received gate signal and producing a second output signal;
• receiving the first and second output signals as inputs to the logic gate;
• and
• producing a logic gate output signal responsive to the received first and second output signals.