Using observability logic for real-time debugging of ASICs

An integrated circuit including logic for testing internal operation of the integrated circuit, the integrated circuit comprising:

• a plurality of internal functional blocks coupled by a plurality of internal buses, wherein the plurality of internal functional blocks and the plurality of internal buses are comprised in the integrated circuit;
• at least one test control input pin comprised on the integrated circuit;
• a set of test output pins comprised on the integrated circuit;
• and
• selection logic comprised in the integrated circuit, wherein the selection logic comprises:
• a plurality of inputs coupled to two or more of the plurality of internal buses;
• at least one select input coupled to receive at least one select signal from the at least one test control input pin;
• and
• an output coupled to the set of test output pins;
• wherein the selection logic is operable to select internal bus signals from one of the two or more internal buses based on the at least one select signal from the at least one test control input pin, wherein the selection logic is configured to output the selected internal bus signals to the set of test output pins.

An integrated circuit including logic for testing internal operation of the integrated circuit, the integrated circuit comprising:

• a plurality of internal functional blocks coupled by a plurality of internal buses, wherein the plurality of internal functional blocks and the plurality of internal buses are comprised in the integrated circuit;
• at least one test control input pin comprised on the integrated circuit;
• a set of test output pins comprised on the integrated circuit;
• and
• selection logic comprised in the integrated circuit, wherein the selection logic comprises:
• a plurality of inputs coupled to two or more of the plurality of internal functional blocks;
• at least one select input coupled to receive at least one select signal from the at least one test control input pin;
• and
• an output coupled to the set of test output pins;
• wherein the selection logic is operable to select internal functional block signals from one of the two or more internal functional blocks based on the at least one select signal from the at least one test control input pin, wherein the selection logic is configured to output the selected internal functional block signals to the set of test output pins.

An application specific integrated circuit, comprising:

• a plurality of functional units;
• a plurality of internal buses connecting the functional units;
• one or more control pins;
• a plurality of test pins;
• and
• multiplexing logic coupled to at least a subset of the plurality of internal buses and the test pins, wherein the multiplexing logic is configured to select one of the plurality of internal buses in response to one or more control signals conveyed to the multiplexing logic from the control pins, wherein the multiplexing logic is configured to output signals from the selected internal bus to the test pins in real-time.

A computer program for testing integrated circuits, wherein the computer program is embodied on a computer-readable medium and comprises instructions executable to:

• receive user-specified information regarding which of a plurality of internal buses on an integrated circuit are to be made available for testing purposes;
• calculate a size of selection logic and number of control signals required to selectively convey the information on the internal buses to a set of test pins;
• and
• provide the results of the calculations to an automated place-and-route routine that determines the physical layout of the integrated circuit.