Quad flat no lead (QFN) grid array package, method of making and memory module and computer system including same

A method of forming an array of electrically conductive elements on an integrated circuit package, the method comprising:

• securing a semiconductor die having a plurality of bond pads on an active surface thereof to a lead frame having a plurality of leads;
• electrically coupling each lead of the plurality of leads at spaced locations with one of at least two different bond pads of the plurality of bond pads;
• and
• severing each lead between the spaced locations to form at least two electrically isolated conductive elements.

A lead frame comprising:

• a plurality of leads, including at least one lead having:
• a first bonding region,
• a second bonding region, and
• a severance region located between the first bonding region and the second bonding region, the severance region being configured to facilitate separation of the first bonding region from the second bonding region.

An integrated circuit package comprising:

• a semiconductor die;
• a plurality of conductive elements arranged in an array, the array including at least a first set of spaced and electrically isolated conductive elements adjacent an outer lateral periphery of the integrated circuit package and at least one other set of spaced and electrically isolated conductive elements inwardly adjacent the first set, the at least two sets of conductive elements being located outside a lateral periphery of the semiconductor die;
• an dielectric encapsulant formed over the semiconductor die and defining the outer lateral periphery of the integrated circuit package, the dielectric encapsulant extending at least partially laterally about the conductive elements and leaving an outer surface of each conductive element exposed;
• and
• a recess in the encapsulant material between at least one conductive element of the first set of conductive elements and at least one adjacent conductive element of the at least one other set of conductive elements.

A memory module comprising:

• a module board configured to be electrically coupled with a higher level of packaging;
• and
• at least one integrated circuit package electrically coupled with the module board, the integrated circuit package comprising:
• a semiconductor die;
• a plurality of conductive elements arranged in an array, the array including at least a first set of spaced and electrically isolated conductive elements adjacent an outer lateral periphery of the integrated circuit package and at least one other set of spaced and electrically isolated conductive elements inwardly adjacent the first set, the at least two sets of conductive elements being located outside a lateral periphery of the semiconductor die;
• an dielectric encapsulant formed over the semiconductor die and defining the outer lateral periphery of the integrated circuit package, the dielectric encapsulant extending at least partially laterally about the conductive elements and leaving an outer surface of each conductive element exposed;
• and
• a recess in the encapsulant material between at least one conductive element of the first set of conductive elements and at least one adjacent conductive element of the at least one other set of conductive elements.

A computer system comprising:

• an input device;
• an output device;
• a processor coupled to the input and output devices;
• and
• a memory module coupled to the processor, the memory module comprising a module board coupled to at least one integrated circuit package comprising:
• a semiconductor die;
• a plurality of conductive elements arranged in an array, the array including at least a first set of spaced and electrically isolated conductive elements adjacent an outer lateral periphery of the integrated circuit package and at least one other set of spaced and electrically isolated conductive elements inwardly adjacent the first set, the at least two sets of conductive elements being located outside a lateral periphery of the semiconductor die;
• an dielectric encapsulant formed over the semiconductor die and defining the outer lateral periphery of the integrated circuit package, the dielectric encapsulant extending at least partially laterally about the conductive elements and leaving an outer surface of each conductive element exposed;
• and
• a recess in the encapsulant material between at least one conductive element of the first set of conductive elements and at least one adjacent conductive element of the at least one other set of conductive elements.

A semiconductor die assembly, comprising:

• a semiconductor die having a plurality of bond pads on an active surface thereof;
• at least one set of mutually spaced conductive elements laterally outboard of at least one peripheral edge of the semiconductor die, and at least another set of mutually spaced conductive elements spaced from and laterally outboard of the at least one set of conductive elements;
• a plurality of wire bonds extending between bond pads of the plurality and conductive elements of the first and second sets;
• and
• a package comprising dielectric material extending over the semiconductor die and wire bonds and having an outer lateral periphery substantially coincident with outer lateral extents of the at least one other set of conductive elements, dielectric material of the package extending at least partially about each of the conductive elements and leaving a surface thereof exposed.

A method of fabricating a semiconductor die assembly, comprising:

• placing a semiconductor die within a plurality of leads extending laterally outwardly from peripheral edges thereof;
• wire bonding bond pads on the semiconductor die to spaced locations on the leads of the plurality;
• transfer molding a dielectric encapsulant over the semiconductor die, wire bonds and leads, leaving undersurfaces of the leads exposed;
• and
• severing the leads between the spaced locations.