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US 2003/0164551 A1Published application
Method and apparatus for flip-chip packaging providing testing capability
AssigneeMicron Technology, Inc.
InventorsTeck Kheng Lee, Wuu Yean Tay, Kian Chai Lee
Life of this patent
Estimating the term…
Abstract
A method and apparatus for increasing the integrated circuit density in a flip chip semiconductor device assembly including an interposer substrate facilitating use with various semiconductor die conductive bump arrangements. The interposer substrate includes a plurality of recesses formed in at least one of a first surface and a second surface of the interposer substrate, wherein the recesses are arranged in a plurality of recess patterns. The interposer substrate also provides enhanced accessibility for test probes for electrical testing of the resulting flip chip semiconductor device assembly.
Claims82
An article for use in mounting at least one flip chip semiconductor die having a plurality of conductive bumps projecting therefrom, comprising:
- an interposer substrate having a first surface and a second surface and comprising a dielectric member having at least one conductive layer thereon comprising a plurality of conductive traces, said interposer substrate including a plurality of recesses formed in at least one of said first and second surfaces, each recess exposing at a bottom thereof at least a portion of a conductive trace, said plurality of recesses arranged in at least a first recess pattern and a second, different recess pattern.
A semiconductor assembly comprising:
- at least one semiconductor die having an active surface and a back surface, said active surface having conductive bumps thereon;
- and
- an interposer substrate having a first surface and a second surface and comprising a dielectric member having at least one conductive layer thereon including a plurality of conductive traces, said interposer substrate including a plurality of recesses formed in at least one of said first and second surfaces, each recess exposing at a bottom thereof at least a portion of one of said conductive traces, said plurality of recesses arranged in at least a first recess pattern and a second, different recess pattern on said interposer substrate, said plurality of conductive bumps of said at least one semiconductor die being received within at least one of said at least a first recess pattern and a second recess pattern.
A method of assembling a semiconductor assembly, the method comprising:
- providing at least one semiconductor die having an active surface and a back surface, said active surface having a plurality of conductive bumps projecting therefrom;
- providing an interposer substrate having a first surface and a second surface and comprising a dielectric member having at least one conductive layer thereon including a plurality of conductive traces, said interposer substrate having a plurality of recesses formed in at least one of said first and second surfaces and exposing at a bottom thereof at least a portion of one of said conductive traces, said recesses arranged in at least a first recess pattern and a second, different recess pattern;
- and
- disposing said plurality of conductive bumps of said at least one semiconductor die in at least one of said at least a first recess pattern and a second recess pattern so that said active surface lies adjacent at least one of said first surface and said second surface of said interposer substrate.
1 more element
A method of fabricating a substrate for mounting at least one semiconductor die in a flip chip arrangement thereto, the method comprising:
- providing an interposer substrate having a first surface and a second surface and a dielectric member having at least one conductive layer thereon including a plurality of conductive traces;
- forming a plurality of recesses in at least one of said first surface and said second surface of said interposer substrate arranged in a first recess pattern and a second, different recess pattern to expose at least portions of said conductive traces at recess bottoms and to a depth into said interposer substrate sufficient to substantially receive therein conductive bumps on an active surface of the at least one semiconductor die.
An electronic system comprising:
- a processor device coupled to an input device and an output device;
- and
- a semiconductor assembly coupled to at least one of said processor device, said input device and said output device, said semiconductor assembly comprising:
- at least one semiconductor die having an active surface and a back surface, said active surface having conductive bumps thereon;
- and
- an interposer substrate having a first surface and a second surface and comprising a dielectric member having at least one conductive layer thereon including a plurality of conductive traces, said interposer substrate including a plurality of recesses formed in at least one of said first and second surfaces, each recess exposing at a bottom thereof at least a portion of one of said conductive traces, said plurality of recesses arranged in at least a first recess pattern and a second, different recess pattern on said interposer substrate, said plurality of conductive bumps of said at least one semiconductor die being received within at least one of said at least a first recess pattern and a second recess pattern.
3 more elements
An interposer substrate, comprising:
- a conductive layer comprising a plurality of conductive traces;
- first and second dielectric members respectively disposed over opposing sides of the conductive layer;
- and
- at least one recess extending from an exterior surface of the first dielectric member to expose a portion of a conductive trace of the plurality;
- and
- at least one recess extending from an exterior surface of the second dielectric member to expose a portion of a conductive trace of the plurality.
3 more elements
An interposer substrate, comprising:
- a dielectric member;
- a first plurality of conductive traces on one side of the dielectric member;
- a second plurality of conductive traces on an opposing side of the dielectric member;
- at least one recess extending from a surface of the dielectric member on the one side thereof to expose a portion of a conductive trace on the opposing side of the dielectric member;
- and
- at least one recess extending from a surface of the dielectric member on the opposing side thereof to expose a portion of a conductive trace on the first side of the dielectric member.
3 more elements
A semiconductor device assembly, comprising:
- a flexible interposer substrate including at least one conductive layer comprising a plurality of conductive traces and at least one dielectric member, the at least one dielectric member having a plurality of recesses extending from an exterior surface of each of two opposing sides of the interposer substrate through the at least one dielectric member to expose portions of conductive traces of the plurality;
- the plurality of recesses being arranged in at least three patterns, at least two of the at least three patterns located on one side of the interposer substrate and at least one of the at least three patterns being located on an opposing side of the interposer substrate in substantial superimposition to at least one of the at least two patterns;
- and
- a least three semiconductor dice of flip-chip configuration having a plurality of conductive elements projecting therefrom, wherein each semiconductor die is operably coupled to at least some of the plurality of conductive traces by conductive elements received in a pattern of recesses;
- the interposer substrate being folded so that at least two of the semiconductor dice operably coupled to conductive traces through patterns of recesses on the one side of the interposer substrate are oriented in substantially superimposed back-to-back relationship between portions of the interposer substrate and at least a third semiconductor die is located in substantial superimposition to the at least two semiconductor dice on the opposing side of the interposer substrate.
2 more elements
Dependencies are inferred from the claim text.