US 2003/0164540 A1 · Semiconductor die packages with recessed interconnecting structures and methods for assembling the same

Abstract

Apparatus and methods relating to semiconductor assemblies. A semiconductor assembly includes an interposer which may be constructed from a flexible material, such as a polyimide tape. A pattern of conductive traces disposed on a first surface of the interposer is in electrical communication with a semiconductor die attached to the first surface. Interconnect recesses accessible on the opposite second surface expose one or more conductive traces. A conductive element, such as a solder ball, disposed substantially within the interconnect recess allows the assembly to be mounted on a substrate or a similar assembly. By substantially containing the conductive element within the interconnect recess, the height of the completed assembly is reduced. Assemblies may be stacked to form multi-die assemblies. Interconnect structures, such as connection pads, or enlarged traces upon the first surface and employed to connect stacked assemblies.

Claims105

Dependent claims

A semiconductor assembly comprising:

a semiconductor die;
a nonrigid interposer comprising an interposer body having a first surface and a second surface, said interposer further comprising:
electrically conductive traces disposed on said first surface, at least one electrically conductive trace being electrically connected to said semiconductor die, and
a connection recess formed in said second surface and passing through said interposer body to expose at least one electrically conductive trace disposed on said first surface;
and
an electrically conductive material disposed substantially within said connection recess, in contact with said at least one exposed electrically conductive trace.

3 more elements

A method of forming a stacked semiconductor assembly comprising:

forming a first semiconductor assembly by
providing a first substrate to form a first interposer body having first and second surfaces,
disposing first electrically conductive traces on said first surface,
forming at least a first connection recess in said second surface and passing through said first interposer body to expose at least one first electrically conductive trace disposed on said first surface,
providing a first semiconductor die,
attaching said first semiconductor die to said first surface in electrical communication with at least one first electrically conductive trace,
disposing an electrically conductive material substantially within said at least first connection recess and in electrically conductive contact with said at least one exposed first electrically conductive trace;
forming a second semiconductor assembly by
providing a second substrate to form a second interposer body having third and fourth surfaces,
disposing second electrically conductive traces on said third surface,
disposing at least a first stacking electrical interconnection structure on said third surface,
forming at least a second connection recess in said fourth surface and passing through said second interposer body to expose at least one second electrically conductive trace disposed on said third surface,
providing a second semiconductor die,
attaching said second semiconductor die to said third surface in electrical communication with at least one second electrically conductive trace disposed on said second surface,
disposing an electrically conductive material substantially within said at least second connection recess and in electrically conductive contact with said at least one exposed one second electrically conductive trace;
and
attaching said first semiconductor assembly to said second semiconductor assembly, such that said at least first recess is aligned with said stacking electrical interconnection structure, and said electrically conductive material disposed within said at least first recess makes electrically conductive contact to said at least first stacking electrical interconnection structure.

14 more elements

A method of forming a stacked semiconductor assembly comprising:

forming a first semiconductor assembly by
providing a first substrate to form a first interposer body having first and second surfaces,
disposing at least a first electrically conductive trace on said second surface,
forming at least a first connection recess in said first surface and passing through said first interposer body to expose at least one first electrically conductive trace disposed on said second surface,
providing a first semiconductor die,
attaching said first semiconductor die to said first surface,
disposing an electrically conductive material substantially within said at least first connection recess and in electrically conductive contact with said at least one exposed first electrically conductive trace;
forming a second semiconductor assembly by
providing a second substrate to form a second interposer body having third and fourth surfaces,
disposing at least a first electrically conductive trace on said third surface,
disposing at least a first stacking electrical interconnection structure on said fourth surface,
forming at least a second connection recess in said third surface and passing through said second interposer body to expose at least one second electrically conductive trace disposed on said fourth surface,
providing a second semiconductor die,
attaching said second semiconductor die to said third surface,
disposing an electrically conductive material substantially within said at least second connection recess and in electrically conductive contact with said at least one exposed second electrically conductive trace;
and
attaching said first semiconductor assembly to said second semiconductor assembly, such that said at
least first recess is aligned with said stacking electrical interconnection structure, and said electrically conductive material disposed within said at least first recess makes electrically conductive contact to said at least first stacking electrical interconnection structure.

15 more elements

Dependencies are inferred from the claim text.

Semiconductor die packages with recessed interconnecting structures and methods for assembling the same

Life of this patent

Semiconductor die packages with recessed interconnecting structures and methods for assembling the same

Life of this patent

Abstract

Claims105