Fuse construction for integrated circuit structure having low dielectric constant dielectric material

A process for forming fuses over a low k dielectric layer in an integrated circuit structure comprising:

• a) providing, over portions of an integrated circuit structure, a layer of low k dielectric material, said layer of low k dielectric material having first openings in an upper surface thereof lined with a first conductive barrier material and filled with copper filler metal to form copper interconnects in said upper surface of said layer of low k dielectric material;
• b) forming a first dielectric layer over said layer of low k dielectric material and over said copper interconnects in said upper surface of said layer of low k dielectric material;
• c) patterning said first dielectric layer to form second openings therein communicating with said copper interconnects in said first openings in said layer of low k dielectric material;
• d) forming a second conductive barrier layer over said first dielectric layer and in contact with said copper interconnects exposed by said patterning of said first dielectric layer;
• e) patterning said second conductive barrier layer to form:
• i) fuse portions between at least some of said copper interconnects;
• and
• ii) a liner over one or more of said copper interconnects;
• f) forming a second dielectric layer over said patterned conductive barrier layer to thereby form a window of second dielectric material above each of said fuse portions.
• g) patterning said second dielectric layer to form third openings therein over at least some of said liners of conductive barrier material over said copper interconnects;
• and
• h) filling said third openings with metal to form metal pads, each in electrical contact with a copper interconnect through a liner.

A process for forming fuses over a low k dielectric layer in an integrated circuit structure comprising:

• a) providing, over portions of an integrated circuit structure, a layer of low k dielectric material, said layer of low k dielectric material having first openings in an upper surface thereof lined with a first conductive barrier material selected from the group consisting of tantalum metal, tantalum nitride, and a dual layer of tantalum metal and tantalum nitride with said tantalum metal in contact with said low k dielectric material, and filled with a copper filler metal, to form copper interconnects in said upper surface of said layer of low k dielectric material;
• b) forming, over said layer of low k dielectric material and over said metal interconnects in said upper surface of said layer of low k dielectric material, a first dielectric layer selected from the group consisting of silicon nitride and silicon carbide;
• c) patterning said first dielectric layer to form second openings therein communicating with said metal interconnects in said first openings in said layer of low k dielectric material;
• d) forming, over said first dielectric layer and in contact with said metal interconnects exposed by said patterning of said first dielectric layer, a second conductive barrier layer comprising a conductive material selected from the group consisting of tantalum, tantalum nitride, a dual layer of tantalum and tantalum nitride, titanium, titanium nitride, and a dual layer of titanium and titanium nitride;
• e) patterning said second conductive barrier layer to form:
• i) fuse portions between at least some of said metal interconnects;
• and
• ii) a liner over one or more of said metal interconnects;
• and
• f) forming, over said patterned conductive barrier layer, a second dielectric layer selected from the group consisting of silicon oxide, silicon nitride, silicon oxynitride, and silicon carbide, to thereby form a window of second dielectric material above each of said fuse portions;
• g) patterning said second dielectric layer to form third openings therein over at least some of said liners of conductive barrier material over said metal interconnects;
• and
• h) filling said third openings with metal to form metal pads, each in electrical contact with a copper metal interconnect through a liner.

An integrated circuit structure which includes fuses formed over a low k dielectric layer comprising:

• a) a layer of low k dielectric material formed over portions of an integrated circuit structure, said layer of low k dielectric material having first openings in an upper surface thereof lined with a first conductive barrier material and filled with a filler metal to form metal interconnects in said upper surface of said layer of low k dielectric material;
• b) a first dielectric layer formed over said layer of low k dielectric material and over said metal interconnects in said upper surface of said layer of low k dielectric material;
• c) second openings patterned in said first dielectric layer, said second openings communicating with said metal interconnects in said first openings in said layer of low k dielectric material;
• d) a second conductive barrier layer formed over said first dielectric layer and in contact with said metal interconnects exposed by said patterning of said first dielectric layer;
• e) fuse portions patterned from said second conductive barrier layer, said fuse portions located between at least some of said metal interconnects;
• f) a liner also patterned from said second conductive barrier layer, said liner located over one or more of said metal interconnects;
• and
• g) a second dielectric layer formed over said patterned conductive barrier layer to thereby form a window of second dielectric material above each of said fuse portions.