Semiconductor device having hetero grain stack gate

A semiconductor device comprising:

• a semiconductor substrate having a surface;
• a gate insulating layer formed over the surface of the semiconductor substrate;
• and
• a gate electrode formed over the gate insulating layer;
• wherein the gate electrode includes a lower poly-SiGe layer having a columnar crystalline structure, an intermediate layer having an random crystalline structure, and an upper poly-Si layer having a columnar crystalline structure.

A method of manufacturing a semiconductor device, comprising:

• depositing a gate insulating layer over a surface of a semiconductor substrate;
• depositing a lower poly-SiGe layer having a columnar crystalline structure over the gate insulating layer;
• depositing an amorphous Si layer over the lower poly-SiGe layer;
• and
• crystallizing the amorphous Si layer to obtain an upper poly-Si layer having a random crystalline structure.

A method of manufacturing a semiconductor device, comprising:

• depositing a gate insulating layer over a surface of a semiconductor substrate;
• depositing a lower poly-SiGe layer having a columnar crystalline structure over the gate insulating layer;
• depositing at least one intermediate layer having an amorphous structure over the lower poly-SiGe layer;
• depositing an amorphous Si layer over the at least one intermediate layer;
• and
• crystallizing the amorphous Si layer to obtain an upper poly-Si layer having a random crystalline structure.

A method of manufacturing a semiconductor device, comprising:

• depositing a gate insulating layer over a surface of a semiconductor substrate;
• depositing a lower poly-SiGe layer having a columnar crystalline structure over the gate insulating layer;
• depositing an amorphous intermediate layer over the lower poly-SiGe layer;
• depositing an upper poly-Si layer over the amorphous intermediate layer;
• and
• crystallizing the amorphous intermediate layer to obtain a crystallized intermediate layer having a random crystalline structure between the lower poly-SiGe layer and the upper poly-Si layer.