Semiconductor device and method of manufacturing the same

A method of manufacturing a semiconductor device comprising the steps of:

• (a) etching a gate electrode material formed on a semiconductor substrate by using a hard mask as a mask, thereby forming at least one gate electrode having said hard mask on an upper surface;
• (b) forming a first resist opening a first channel region of said semiconductor substrate;
• (c) carrying out first ion implantation by using, as masks, said gate electrode having said hard mask on said upper surface and said first resist;
• (d) removing said hard mask by etching using said first resist as a mask after said step (c);
• (e) removing said first resist;
• (f) forming a second resist opening a second channel region of said semiconductor substrate;
• (g) carrying out second ion implantation by using, as masks, said gate electrode having said hard mask on said upper surface and said second resist;
• (h) removing said hard mask by etching using said second resist as a mask after said step (g);
• and
• (i) removing said second resist.

A method of manufacturing a semiconductor device comprising the steps of:

• (a) etching a gate electrode material formed on a semiconductor substrate by using a hard mask as a mask, thereby forming at least one gate electrode having said hard mask on an upper surface;
• (b) forming a first resist opening a first channel region of said semiconductor substrate;
• (c) carrying out first ion implantation by etching using, as masks, said gate electrode having said hard mask on said upper surface and said first resist;
• (d) removing said first resist;
• (e) forming a second resist opening a second channel region of said semiconductor substrate;
• (f) carrying out second ion implantation by using, as masks, said gate electrode having said hard mask on said upper surface and said second resist;
• (g) removing said second resist;
• and
• (h) removing said hard mask by etching after said steps (a) to (g).

A method of manufacturing a semiconductor device comprising a peripheral circuit having a transistor and a cell array having a memory cell, comprising the steps of:

• (a) etching a gate electrode material formed on a semiconductor substrate by using a hard mask as a mask, thereby forming a first gate electrode of said transistor and a second gate electrode of said memory cell which have said hard mask on upper surfaces;
• (b) forming a resist opening a predetermined channel region in said peripheral circuit and a contact formation region in said cell array;
• (c) carrying out ion implantation by using, as masks, said first gate electrode and said second gate electrode which have said hard mask on said upper surfaces, and said resist;
• and
• (d) removing said hard mask by etching using said resist as a mask after said step (c).

A semiconductor device comprising:

• a first gate electrode formed on a semiconductor substrate;
• a side wall formed on a side surface of said first gate electrode;
• and
• a source-drain region formed in said semiconductor substrate and having a low impurity concentration region provided so as to sandwich said gate electrode and a high impurity concentration region provided outside said low impurity concentration region so as to sandwich said gate electrode;
• wherein a width of said side wall is smaller than a space between said first gate electrode and said high impurity concentration region;
• and
• a contact is formed on an upper surface of said source-drain region.

A semiconductor device comprising, on a semiconductor substrate, a peripheral circuit having a transistor and a cell array having a plurality of memory cells,

• wherein said transistor of said peripheral circuit includes:
• a first gate electrode;
• a side wall formed on a side surface of said first gate electrode;
• and
• a source-drain region formed in said semiconductor substrate and having a low impurity concentration region provided so as to sandwich said gate electrode and a high impurity concentration region provided outside said low impurity concentration region so as to sandwich said gate electrode,
• wherein a width of said side wall is smaller than a space between said first gate electrode and said high impurity concentration region;
• a contact is formed on an upper surface of said source-drain region;
• and
• said memory cell of said cell array includes:
• a second gate electrode;
• and
• a hard mask formed on an upper surface of said second gate electrode, and
• said hard mask is formed in only a region of said upper surface of said second gate electrode other than a region in which a contact is to be formed.