Method for forming raised structures by controlled selective epitaxial growth of facet using spacer

A method of forming a raised structure on a substrate, comprising the step of:

• forming an epitaxial layer of monocrystalline silicon on the substrate;
• forming a layer of insulative material over the epitaxial layer;
• removing a portion of the insulative layer to leave only an exposed top surface of the epitaxial layer;
• forming another epitaxial layer of monocrystalline silicon on the epitaxial layer;
• and
• repeating the steps of forming the insulative layer, removing a portion of the insulative layer, and growing an epitaxial layer, until the vertical structure reaches a desired height, with the uppermost epitaxial layer having an insulated top surface.

A method of forming a vertical structure on a substrate, comprising the steps of:

• depositing a first epitaxial layer on the substrate, the first epitaxial layer comprising a horizontally oriented surface defining a facet;
• forming a layer of an insulative material over the first epitaxial layer;
• removing a portion of the insulative layer to expose the horizontal surface of the epitaxial layer;
• depositing a second epitaxial layer on the exposed surface of the first epitaxial layer;
• the second epitaxial layer comprising a horizontally oriented surface defining a facet;
• and
• forming a layer of an insulative material over the second epitaxial layer.

A method of controlling growth of an epitaxial film to form a vertical structure on a substrate, comprising the steps of:

• providing a substrate having an elevated structure disposed thereon, the elevated structure having an overlying insulative layer;
• forming a first epitaxial layer of monocrystalline silicon on the substrate adjacent to the elevated structure;
• forming an insulative layer over the first epitaxial layer;
• removing a horizontal surface of the insulative layer to expose only a top surface of the first epitaxial layer;
• forming a second epitaxial layer of monocrystalline silicon over the first epitaxial layer;
• and
• repeating the foregoing steps until the vertical structure is at a desired height.

A method of forming an elevated structure on a substrate in a semiconductor processing, comprising the steps of:

• providing a semiconductor substrate comprising monocrystalline silicon;
• growing a first epitaxial layer on the substrate until a horizontally-oriented facet is formed;
• forming an insulative layer over the first epitaxial layer;
• removing the insulative layer to expose only a horizontal surface of the first epitaxial layer;
• growing a second epitaxial layer on the first epitaxial layer until a horizontally-oriented facet is formed;
• and
• repeating the steps of forming the insulative layer, removing a portion of the insulative layer, and growing an epitaxial layer, until the elevated structure is at a desired height.

A method of forming a raised structure on a silicon substrate, comprising the steps of:

• selectively growing a first epitaxial layer of monocrystalline silicon on the substrate;
• forming a layer of an insulative material over the first epitaxial layer;
• and
• selectively growing one or more additional epitaxial layers of monocrystalline silicon to form the raised structure to a predetermined height, each epitaxial layer having insulated sidewalls and a top surface.

A method of fabricating an epitaxial structure on a substrate, comprising the steps of:

• forming a first epitaxial layer of monocrystalline silicon on the substrate;
• annealing the epitaxial layer to form an insulative film thereover;
• etching the insulative film to expose only a horizontal surface of the first epitaxial layer;
• and
• repeating the foregoing steps to form additional overlying epitaxial layers until a vertical structure having a desired height is reached, the vertical structure comprising multiple epitaxial layers having only insulated sidewalls, with an uppermost epitaxial layer having insulated sidewalls and an insulated top surface.

A method for forming a DRAM cell on a silicon substrate, comprising the steps of:

• forming a vertical gate structure on the substrate by the steps of:
• forming a first epitaxial layer of monocrystalline silicon on the substrate;
• forming a layer of an insulative material over the first epitaxial layer;
• removing a portion of the insulative layer to expose only a horizontal surface of the first epitaxial layer;
• and
• repeating the foregoing steps to form one or more additional overlying epitaxial layers until the gate structure is of a desired height, the gate structure comprising multiple overlying epitaxial layers having insulated sidewalls, and an uppermost epitaxial layer having an insulated sidewalls and a horizontal surface;
• and
• forming source and drain regions adjacent to the gate structure.

A method of forming an elevated source or drain structure on a substrate having a transistor gate disposed thereon, the method comprising the steps of:

• selectively growing, while doping, a first epitaxial layer of monocrystalline silicon on the substrate adjacent to the transistor gate;
• depositing a layer of an insulative material onto the first epitaxial layer;
• removing only the horizontal surface of the insulative layer;
• growing additional overlying epitaxial layers according to the foregoing steps until the elevated source or drain structure reaches a desired height;
• each epitaxial layer having insulated sidewalls;
• wherein, upon growing an uppermost epitaxial layer and depositing the insulative layer thereon, no removal step is performed such that the uppermost epitaxial layer comprises insulated sidewalls and an insulated horizontal surface.

A method of forming an elevated source or drain structure on a substrate having a transistor gate formed thereon,

• selectively growing a first epitaxial layer of monocrystalline silicon on the substrate adjacent to the gate;
• depositing a layer of an insulative material onto the first epitaxial layer;
• removing only the horizontal surface of the insulative layer;
• growing additional overlying epitaxial layers according to the foregoing steps until the elevated source or drain structure reaches a desired height;
• each epitaxial layer having insulated sidewalls and an uppermost epitaxial layer having an exposed top surface;
• doping the uppermost epitaxial layer with a conductivity enhancing dopant by ion implantation;
• and
• depositing a layer of an insulative material onto the uppermost epitaxial layer.

A method of forming an elevated transistor in a semiconductive wafer processing comprising the steps of:

• providing a semiconductor substrate;
• forming a buried drain in the substrate;
• forming an elevated gate over the buried drain by the steps of:
• forming a first epitaxial layer over the buried drain;
• forming an insulative layer over the first epitaxial layer;
• removing a portion of the insulative layer to expose only a horizontal surface of the first epitaxial layer;
• forming a second epitaxial layer over the first epitaxial layer;
• forming an insulative layer over the second epitaxial layer;
• and
• repeating the foregoing steps to form additional overlying epitaxial layers to form a pillar-like structure having a desired height;
• each epitaxial layer having insulated sidewalls, and the uppermost epitaxial layer having an exposed horizontal surface;
• and
• forming a source region onto the gate by forming at least one epitaxial layer over the uppermost epitaxial layer, while doping.

A method of semiconductive wafer processing, comprising forming an elevated transistor by the steps of:

• providing a semiconductor substrate;
• forming a buried drain in the substrate;
• forming an elevated gate over the buried drain, the gate comprising multiple overlying epitaxial layers in a vertical orientation with each epitaxial layer having insulative sidewalls;
• and
• forming a source region over the uppermost epitaxial layer of the gate, the source region comprising one or more epitaxial layers, each layer having insulative sidewalls and the uppermost layer having an insulated top surface.

A transistor in a semiconductor device, comprising:

• a transistor gate formed on a semiconductive region of substrate;
• and
• elevated source/drain diffusion regions formed on the semiconductive region adjacent to the transistor gate, and extending in a vertical plane from the substrate;
• each of the source/drain diffusion regions covered by a layer of insulative material and comprising at least two overlying layers of epitaxially grown silicon.