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US 2003/0164510 A1Published application
Redundancy architecture for repairing semiconductor memories
AssigneeElpida Memory, Inc.
InventorChiaki Dono
Life of this patent
Estimating the term…
Abstract
A redundancy architecture for improving the throughput of testing and repairing the semiconductor memory after packaging. A memory device is composed of a memory cell array including memory cells and first redundant cells, a data comparator comparing read data received from the memory cell array with anticipated data provided by an external tester to produce a data mismatch signal, a redundancy mapping circuit responsive to the data mismatch signal for detecting a defective address of the memory cell array, a nonvolatile memory storing the detected defective address, and a redundancy circuitry repairing the memory cell array by replacing ones of the memory cells associated with the defective address with the first redundant cells.
Claims22
A memory device comprising:
- a memory cell array including memory cells and first redundant cells;
- a data comparator comparing read data received from said memory cell array with anticipated data provided by an external tester) to produce a data mismatch signal;
- a redundancy mapping circuit responsive to said data mismatch signal for detecting a defective address of said memory cell array;
- a nonvolatile memory storing said detected defective address;
- and
- a redundancy circuitry repairing said memory cell array by replacing ones of said memory cells associated with said defective address with said first redundant cells.
3 more elements
A memory device comprising:
- a memory cell array including:
- primary memory cells arranged in primary rows, and
- redundant memory cells arranged in redundant rows;
- a plurality of nonvolatile memories respectively storing defective row addresses, wherein said plurality of nonvolatile memories respectively stores NVRAM enable bits representative of whether said defective row addresses respectively stored in said nonvolatile memories are effective;
- a redundancy circuitry repairing said memory cell array by replacing one of said primary rows associated with said defective address with said redundant rows,
- a data comparator comparing read data received from said memory cell array to anticipated data provided by an external tester to produce a data mismatch signal;
- a redundancy mapping circuit responsive to said data mismatch signal for detecting a defective row address and selecting one of said plurality of nonvolatile memories in response to said NVRAM enable bits, wherein said selected one of said plurality of nonvolatile memories stores said detected defective row address.
4 more elements
A memory device comprising:
- a memory cell array including memory cells and redundant cells;
- a data comparator comparing read data received from said memory cell array to anticipated data provided by an external tester to produce a data mismatch signal;
- a redundancy mapping circuit responsive to said data mismatch signal for detecting a defective address of said memory cell array;
- a nonvolatile memory storing said detected defective address;
- a volatile latch circuit latching said defective address from said nonvolatile memory;
- an address compare circuit comparing a received address with said latched defective address to produce an address hit signal, and
- a decoder circuitry selecting, in response to said address hit signal, said redundant cells instead of ones of memory cells associated with said received address.
4 more elements
A method of testing and repairing a memory device comprising:
- providing said memory device with a test pattern including test addresses and anticipated data for said test addresses by an external tester;
- comparing read data from memory cells identified by said test addresses with said anticipated data to detect a defective address by a circuitry implemented within said memory device;
- storing said defective address in a nonvolatile memory implemented within said memory device;
- and
- replacing memory cells associated with said defective address with redundant cells based on said defective address stored in said nonvolatile memory by a redundancy circuitry implemented within said memory device.
2 more elements
A method of testing and repairing a plurality of memory devices comprising:
- concurrently providing each of said memory device with a same test pattern including test addresses and anticipated data for said test addresses by an external tester;
- comparing read data from memory cells identified by said test addresses with said anticipated data to detect a defective address by a circuitry implemented within each of said plurality of memory devices;
- storing said defective address in a nonvolatile memory implemented within each of said memory device;
- and
- replacing memory cells associated with said defective address with redundant cells based on said defective address stored in said nonvolatile memory by a redundancy circuitry implemented within each of said memory device.
2 more elements
A method of operating a memory device including a nonvolatile memory circuitry storing defective addresses and an address compare circuit, said method comprising:
- providing said memory device with a test pattern including test addresses and anticipated data for said test addresses by an external tester;
- comparing read data from memory cells identified by said test addresses with said anticipated data to detect a defective address by a circuitry implemented within said memory device;
- comparing by said address compare circuit said detected defective address with said defective addresses stored in said nonvolatile memory circuitry;
- additionally storing said detected defective address in said nonvolatile memory circuitry when said detected defective address matches none of said defective addresses stored in said nonvolatile memory circuitry;
- comparing by said address compare circuit a received address with said defective addresses stored in said nonvolatile memory circuitry;
- selecting redundant memory cells instead of memory cells identified with said received address when said received address matches one of said defective addresses stored in said nonvolatile memory circuitry.
3 more elements
A method of operating a memory device including a nonvolatile memory circuitry, a volatile latch circuit and an address compare circuit, said method comprising:
- providing said memory device with a test pattern including test addresses and anticipated data for said test addresses by an external tester;
- comparing read data from memory cells identified by said test addresses with said anticipated data to determine a defective address by a circuitry implemented within said memory device;
- temporarily storing said defective address in said latch circuit;
- transferring said temporarily stored defective address from said latch circuit to said nonvolatile memory circuitry;
- storing said transferred defective address in said nonvolatile memory circuitry;
- latching said defective address stored in said nonvolatile memory circuitry by said latch circuit;
- comparing by said address compare circuit a received address with said latched defective address;
- and
- selecting redundant memory cells instead of memory cells identified with said received address when said received address matches one of said latched defective address.
6 more elements
Dependencies are inferred from the claim text.