System and method for generating integrated circuit boundary register description data

A system for generating a boundary-scan description language file for an integrated circuit, comprising:

• means for creating a flat netlist that describes said integrated circuit, wherein said flat netlist comprises connectivity information regarding leaf cells within said integrated circuit;
• means for determining and storing a name provided for each joint test action group register located within said integrated circuit, from said created flat netlist;
• means for determining relationships between each joint test action group register located within said integrated circuit and at least one input/output pin located within said integrated circuit, from said created flat netlist, and for storing a description of said relationships;
• and
• means for creating said boundary-scan description language file from said stored names of each joint test action group and said stored description of said relationship between said joint test action group register and said input/output pin.

A system for generating a boundary-scan description language file for an integrated circuit, comprising:

• a memory;
• software stored within said memory defining functions to be performed by said system;
• and
• a processor configured by said software to perform the steps of:
• creating a flat netlist that describes said integrated circuit, wherein said flat netlist comprises connectivity information regarding leaf cells within said integrated circuit;
• determining and storing a name provided for each joint test action group register located within said integrated circuit, from said created flat netlist;
• determining relationships between each joint test action group register located within said integrated circuit and at least one input/output pin located within said integrated circuit, from said created flat netlist, and storing a description of said relationships;
• and
• creating said boundary-scan description language file from said stored names of each joint test action group and said stored description of said relationship between said joint test action group register and said input/output pin.