Semiconductor device having wide wiring pattern in outermost circuit
AssigneeDenso Corporation
InventorsTaku Iida, Satoru Kawamoto, Toshiaki Yagura
Life of this patent
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Abstract
A semiconductor electronic part, having a lot of bumps allocated in a checkered pattern, is solder-mounted on a multilayer circuit board. In the multilayer circuit board, a first wiring pattern linked with a first land is finer than a second wiring pattern linked with a second land. Only one first wiring pattern is passable between lands. The second lands are allocated in the outmost line on the uppermost layer of the multilayer circuit board. In the semiconductor electronic part, bumps connectable with the second lands are allocated in the outermost line.
Claims7
A semiconductor device in which a semiconductor electronic part having connecting terminals in a checkered pattern is solder-mounted on a multilayer circuit board having wiring patterns and lands, the semiconductor device comprising:
- a first wiring pattern forming a part of the wiring patterns;
- a first land forming a part of the lands and linked with the first wiring pattern;
- a first terminal forming a part of the terminals and connectable with the first land;
- a second wiring pattern forming a part of the wiring patterns and wider than the first wiring pattern;
- a second land forming a part of the lands and linked with the second wiring pattern;
- and
- a second terminal forming a part of the terminals and connectable with the second land,
- wherein two of the adjoining lands are spaced from each other to allow only one of the first wiring patterns to pass through,
- wherein the second land is formed in at least the first outermost line of at least the first uppermost layer of the multilayer circuit board, and
- wherein the second terminal is allocated in at least the first outermost line among the terminals.
A semiconductor device in which a semiconductor electronic part having connecting terminals in a checkered pattern is solder-mounted on a multilayer circuit board having wiring patterns and lands, the semiconductor device comprising:
- a first wiring pattern forming a part of the wiring patterns;
- a first land forming a part of the lands and linked with the first wiring pattern;
- a first terminal forming a part of the terminals and connectable with the first land;
- a second wiring pattern forming a part of the wiring patterns and wider than the first wiring pattern;
- a second land forming a part of the lands and linked with the second wiring pattern;
- and
- a second terminal forming a part of the terminals and connectable with the second land,
- wherein two of the adjoining lands are spaced from each other to allow only one of the first wiring patterns to pass through,
- wherein the second terminals are allocated in at least both of the first outermost line and the third outmost line among the terminals,
- wherein the second terminal that is allocated in the first outermost line is connectable with the second land that is allocated in the first outermost line of the first uppermost layer of the multilayer circuit board, and
- wherein the second terminal that is allocated in the third outermost line is connectable with the second land that is allocated in the first outermost line of the second uppermost layer of the multilayer circuit board.
Dependencies are inferred from the claim text.