Variable stage ratio buffer insertion for noise optimization in a logic network
AssigneeCadence Design Systems, Inc.
InventorKenneth Hing Key Tseng
Life of this patent
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Abstract
A buffer for use in a logic circuit comprises input and output nodes. A first inverter having a first device size is coupled to the input node. A second inverter is coupled in series with the first inverter and with the output node. The second inverter having a second device size at least six times greater than the first device size. It is emphasized that this abstract is provided to comply with the rules requiring an abstract that will allow a searcher or other reader to quickly ascertain the subject matter of the technical disclosure. It is submitted with the understanding that it will not be used to interpret or limit the scope or meaning of the claims. 37 CFR 1.72(b).
Claims29
A buffer for noise rejection in a logic circuit comprising:
- an input node;
- an output node;
- a first inverter coupled to the input node, the first inverter having a first device size;
- a second inverter coupled to the first inverter and the output node, the second inverter having a second device size at least six times greater than the first device size.
A computer-aided method for design of a logic network comprising:
- extracting parametric information from a layout of the logic network;
- analyzing the logic network to identify a crosstalk-induced glitch at a node of a signal path in the logic network;
- inserting a buffer at the node that functions to suppress a magnitude of the crosstalk-induced glitch, the buffer including first and second inverters coupled in series, the first and second inverters respectively having a device size ratio of 1:6 or larger.
A computer-aided method for design of a logic network comprising:
- identifying a crosstalk-induced glitch at an input node of a logic state device in a signal path of the logic network, the crosstalk-induced glitch having a magnitude sufficient to disturb a logic level at the input node;
- inserting a buffer in the signal path at the input node so as to suppress the magnitude of the crosstalk-induced glitch, the buffer including first and second inverters coupled in series, the first and second inverters respectively having a device size ratio of 1:6 or larger.
A computer-readable storage medium having a configuration that represents data and instructions that cause a processor to:
- extract parametric information from a layout of a logic network;
- analyze the logic network to identify an input node of a logic state device in a signal path of the logic network where a crosstalk-induced glitch occurs;
- modify the layout by insertion of a buffer in the signal path at or just prior to the input node, the buffer including first and second inverters coupled in series, the first and second inverters respectively having a device size ratio of 1:6 or larger.
Dependencies are inferred from the claim text.