Method for checking an integrated electrical circuit

A method for checking an integrated electrical circuit to be described by a layout including circuit network descriptions of the integrated electrical circuit, each of the circuit network descriptions being in a form of one of a file and a part of a file on a memory unit of a computer system and each of the circuit network descriptions having at least one polygon each representing one circuit element of the integrated electrical circuit and information regarding electrical characteristics of circuit elements of the integrated electrical circuit, the layout having instantiations of at least one circuit network description and information about a geometrical shape and a configuration of the instantiations with respect to one another, the layout being extending over a number of levels disposed one above another, the layout being described by a raw data structure associating each instantiation of a circuit network description with only one polygon data structure, which comprises:

• carrying out the following steps with a computer program:
• a) selecting a circuit network description from the layout;
• b1) selecting a highest level from the layout;
• b2) determining the instantiations of the selected circuit network description on the level selected in step b1);
• b3) forming difference polygons by comparing the instantiations on the level selected in step b1) in pairs;
• b4) forming variants for instantiations having different difference polygons;
• b5) checking the difference polygons acting on circuit network descriptions in a next-lower level;
• b6) assigning the instantiations to the variants formed in step b4) based upon the difference polygons;
• c1) selecting the next-lower level;
• c2) determining the instantiations of the selected circuit network description on the level selected in step c1);
• c3) forming difference polygons by comparing the instantiations on the level selected in step c1) in pairs;
• c4) combining the difference polygons formed in step c3) with the previously formed difference polygons;
• c5) checking the difference polygons acting on circuit network descriptions in a next-lower level;
• c6) assigning the instantiations to the variants already having been formed based upon the difference polygons;
• c7) forming further variants for instantiations having difference polygons differing from the difference polygons combined in step c4);
• c8) assigning the instantiations found in step c7) to the variants formed in step c7);
• d1) repeating steps b1) to b5), c1) and c8) in a loop until a lowest level in the layout has been reached;
• e) forming a new data structure associating the circuit network description with only one polygon data structure, geometrical differences between the instantiations of the same circuit network description being taken into account by variants in the polygon data structure;
• f) storing the formed new data structure as one of a file and a part of a file on the memory unit of the computer system;
• and
• g) checking the layout of the integrated electrical circuit using the new data structure stored in step f) for faults caused by a configuration of the integrated electrical circuit.

A method for checking an integrated electrical circuit having circuit elements with electrical characteristics, which comprises:

• providing a layout describing the integrated electrical circuit, the layout:
• having circuit network descriptions of the integrated electrical circuit, each of the circuit network descriptions:
• being in the form of one of a file and a part of a file on a memory unit of a computer system;
• having at least one polygon each representing one of the circuit elements;
• and
• having information about the electrical characteristics of the circuit elements;
• having at least one of a plurality of instantiations of at least one circuit network description, the instantiations having a geometrical shape and a configuration;
• having information about the geometrical shape and the configuration of the instantiations with respect to one another;
• and
• being described by a raw data structure associating each instantiation of a circuit network description with only one of a plurality of polygon data structures;
• and
• carrying out the following steps with a computer program:
• a) selecting a circuit network description from the layout;
• b) determining the instantiations of the circuit network description in the layout;
• c) determining the respectively geometrically identical and geometrically different instantiations of the circuit network descriptions by analyzing the polygon data structures;
• d) forming variants for the instantiations of the circuit network descriptions and assigning the instantiations to the variants, geometrically different ones of the instantiations being combined into respectively different variants and geometrically matching ones of the instantiations being combined into respectively identical variants;
• e) forming a new data structure associating the circuit network description with only one polygon data structure, geometrical differences between the instantiations of the same circuit network description being taken into account by variants in the polygon data structure;
• f) storing the formed new data structure as one of a file and a part of a file on the memory unit of the computer system;
• and
• g) checking the layout of the integrated electrical circuit using the new data structure stored in step f) for faults caused by a configuration of the integrated electrical circuit.

A method for checking an integrated electrical circuit having circuit elements with electrical characteristics, which comprises:

• providing a layout describing the integrated electrical circuit, the layout:
• having circuit network descriptions of the integrated electrical circuit, each of the circuit network descriptions:
• being in the form of one of a file and a part of a file on a memory unit of a computer system;
• having at least one polygon each representing one of the circuit elements;
• and
• having information about the electrical characteristics of the circuit elements;
• having at least one of a plurality of instantiations of at least one circuit network description, the instantiations having a geometrical shape and a configuration;
• having information about the geometrical shape and the configuration of the instantiations with respect to one another;
• extending over a number of levels disposed one above another;
• and
• being described by a raw data structure associating each instantiation of a circuit network description with only one of a plurality of polygon data structures;
• and
• carrying out the following steps with a computer program:
• a) selecting a circuit network description from the layout;
• b1) selecting a highest level from the layout;
• b2) determining the instantiations of the selected circuit network description on the level selected in step b1);
• b3) forming difference polygons by comparing the instantiations on the level selected in step b1) in pairs;
• b4) forming variants for instantiations having different difference polygons;
• b5) checking the difference polygons acting on circuit network descriptions in a next-lower level;
• b6) assigning the instantiations to the variants formed in step b4) based upon the difference polygons;
• c1) selecting the next-lower level;
• c2) determining the instantiations of the selected circuit network description on the level selected in step c1);
• c3) forming difference polygons by comparing the instantiations on the level selected in step c1) in pairs;
• c4) combining the difference polygons formed in step c3) with the previously formed difference polygons;
• c5) checking the difference polygons acting on circuit network descriptions in a next-lower level;
• c6) assigning the instantiations to the variants already having been formed based upon the difference polygons;
• c7) forming further variants for instantiations having difference polygons differing from the difference polygons combined in step c4);
• c8) assigning the instantiations found in step c7) to the variants formed in step c7);
• d1) repeating steps b1) to b5), c1) and c8) in a loop until a lowest level in the layout has been reached;
• e) forming a new data structure associating the circuit network description with only one polygon data structure, geometrical differences between the instantiations of the same circuit network description being taken into account by variants in the polygon data structure;
• f) storing the formed new data structure as one of a file and a part of a file on the memory unit of the computer system;
• and
• g) checking the layout of the integrated electrical circuit using the new data structure stored in step f) for faults caused by a configuration of the integrated electrical circuit.