Method for designing semiconductor integrated circuit and computing program for semiconductor integrated circuit

A method for designing a semiconductor integrated circuit comprising;

• a net list-making step of making a net list of a semiconductor integrated circuit,
• a first check step of performing a first signal integrity check of said semiconductor integrated circuit on the basis of said net list, and
• a second layout step of making a layout patern of said semiconductor integrated circuit on the basis of said net list after said first check step.

A method for designing a semiconductor integrated circuit comprising;

• a third layout step of determining a first layout patern of a semiconductor integrated circuit,
• a first layout correcting step of making a second layout patern by correcting said first layout patern so as to solve a setup time violation of said semiconductor integrated circuit and a signal integrity violation of said semiconductor integrated circuit, and
• a second layout-correcting step of correcting said second layout patern so as to solve a holding time violation of said semiconductor integrated circuit after said first layout correcting step.

A computing program for designing a semiconductor integrated circuit comprising;

• a net list-making step of making a net list of a semiconductor integrated circuit,
• a first check step of performing a first signal integrity check of said semiconductor integrated circuit on the basis of said net list, and
• a second layout step of making a layout patern of said semiconductor integrated circuit on the basis of said net list after said first check step.

A computing program for designing a semiconductor integrated circuit comprising;

• a third layout step of determining a first layout patern of a semiconductor integrated circuit,
• a first layout correcting step of making a second layout patern by correcting said first layout patern so as to solve a setup time violation of said semiconductor integrated circuit and a signal integrity violation of said semiconductor integrated circuit, and
• a second layout-correcting step of correcting said second layout patern so as to solve a holding time violation of said semiconductor integrated circuit after said first layout correcting step.