Method for generating test signals for an integrated circuit and test logic unit
AssigneeInfineon Technologies AG
InventorsVolker Kilian, Richard Roth
Life of this patent
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Abstract
To generate test signals by a test logic unit on a semiconductor wafer, the test signals being used to check specific functions and/or parameters of an integrated circuit on the semiconductor wafer, at least two test signals are provided substantially simultaneously by the test logic unit and are subsequently serialized to generate a multiplexed test signal sequence with a data rate required for testing.
Claims31
A method for generating test signals with a test logic unit on a semiconductor chip to check at least one of specific functions and parameters of an integrated circuit on the semiconductor chip with the test signals, which comprises:
- providing at least two test signals substantially simultaneously with the test logic unit;
- and
- subsequently serializing the at least two test signals to generate a multiplexed test signal sequence with a data rate required for testing.
A method for checking at least one of specific functions and parameters of an integrated circuit on a semiconductor chip with test signals, which comprises:
- generating at least two test signals with a test logic unit on the semiconductor chip;
- providing the at least two test signals substantially simultaneously with the test logic unit and subsequently serializing the at least two test signals to generate a multiplexed test signal sequence with a data rate required for testing;
- and
- checking the at least one of specific functions and parameters of the integrated circuit with the at least two test signals.
A method for generating test signals with a test logic unit on a semiconductor chip to check at least one of specific functions and parameters of an integrated circuit with the test signals, which comprises:
- providing an integrated circuit on the semiconductor chip;
- providing at least two test signals substantially simultaneously with the test logic unit;
- and
- subsequently serializing the at least two test signals to generate a multiplexed test signal sequence with a data rate required for testing.
A test logic unit for generating test signals on a semiconductor chip used to check at least one of specific functions and parameters of an integrated circuit on the semiconductor chip, comprising:
- a multiplexer;
- at least two algorithmic function generators connected in parallel and connected to said multiplexer, said at least two algorithmic function generators generating test signals including at least two substantially simultaneously generated test signals;
- and
- said multiplexer serializing said at least two test signals and outputting a multiplexed test signal sequence with a given testing data rate.
A test logic unit for generating test signals on a semiconductor chip used to check at least one of specific functions and parameters of an integrated circuit on the semiconductor chip, comprising:
- a multiplexer;
- at least two algorithmic function generators connected in parallel, each of said at least two algorithmic function generators being connected to said multiplexer and generating test signals including at least two substantially simultaneously generated test signals;
- and
- said multiplexer serializing said at least two test signals and outputting a multiplexed test signal sequence with a given testing data rate.
Dependencies are inferred from the claim text.