Low cost built-in self test state machine for general purpose RAM testing
AssigneeIntel Corporation
InventorEric R. Wehage
Life of this patent
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Abstract
A system and method for creating a built-in self-testing (BIST) state machine to test random access memories (RAMs) are disclosed. The BIST state machine can be simplified to a simple four-state state machine while accommodating a large group of test suites by programming each state to have the capability of performing one of four necessary operations. These operations include a write operation, a read operation, a read/write operation and a null operation. Further bits and signals can be added to the state machine to enable an even larger array of test suites to be performed.
Claims20
An integrated circuit comprising a built-in self test (BIST) state machine, having:
- a plurality of states to conduct a plurality of tests for a random access memory (RAM), each state capable of performing a null operation, a write operation, a read operation, and a read/write operation;
- a command register coupled to the plurality of states and storing a test pattern for use with the plurality of states;
- and
- an address counter coupled to the plurality of states to determine a test location in the RAM.
A method, comprising:
- feeding a test pattern to a command register in a built-in self testing (BIST) state machine;
- reading a test location in a random access memory (RAM) from an address counter;
- and
- applying the commands of the test pattern to the test location using a plurality of states, each of the plurality of states being configurable to perform a null operation, a write operation, a read operation, and a read/write operation.
A machine-readable storage medium tangibly embodying a sequence of instructions executable by the machine to perform a method comprising:
- feeding a test pattern to a command register in a built-in self testing (BIST) state machine;
- reading a test location in a random access memory (RAM) from an address counter;
- and
- applying the commands of the test pattern to the test location using a plurality of states, each of the plurality of states being configurable to perform a null operation, a write operation, a read operation, and a read/write operation.
Dependencies are inferred from the claim text.