Data processor
AssigneeSanyo Electric Co., Ltd.
InventorsTomofumi Watanabe, Yuuichiro Tsukamizu
Life of this patent
Estimating the term…
Abstract
A CD-ROM decoder for processing digital data while buffering the digital data in a buffer RAM. The CD-ROM decoder includes a host interface for storing the digital data in the buffer RAM. An EDC processing circuit generates an error detection code using the digital data read from the buffer RAM in a block unit. An ECC processing circuit generates an error correction code with the digital data and the error detection code. An internal RAM stores the digital data and adds the error detection code and the error correction code to the digital data when storing the digital data. A digital signal processor outputs the digital data, the error detection code, and the error correction code that are stored in the internal RAM in a block unit.
Claims11
A data processor for processing digital data while buffering the digital data in a buffer memory, the data processor comprising:
- a first interface which stores the digital data in the buffer memory;
- a detection code processing circuit which receives the digital data when read from the buffer memory in a block unit and which generates an error detection code that is added to the read digital data;
- a correction code processing circuit which generates an error correction code with the digital data and the error detection code;
- an internal memory circuit which stores the digital data, the error detection code and the error correction code while adding the error detection code and the error correction code to the digital data;
- and
- a second interface which outputs the digital data, to which the error detection code and the error correction code are added, stored in the internal memory circuit in a block unit.
A method for processing digital data while buffering the digital data in a buffer memory, the method comprising:
- storing the digital data in the buffer memory;
- reading the digital data from the buffer memory in a block unit and generating an error detection code that is added to the read digital data;
- generating an error correction code with the digital data and the error detection code;
- storing the digital data, the error detection code and the error correction code in an internal memory circuit while adding the error detection code and the error correction code to the digital data;
- and
- outputting the digital data, to which the error detection code and the error correction code are added, stored in the internal memory circuit.
Dependencies are inferred from the claim text.