Data transmission across asynchronous clock domains

System for use in transmitting data and related control information from a first processing section to a second processing section, the first processing section being in a first clock domain, the second processing section being in a second clock domain, the system comprising:

• a first logic section that may generate respective identification information that may be associated with and used to identify respective types of information represented by respective data and respective related control information;
• and
• memory that may receive and store, at a first clock rate used in the first clock domain, the respective data and the respective related control information, the memory also storing, in association with the respective data and the respective related control information, the respective identification information generated by the first logic section that may be used to identify the respective types of information represented by the respective data and the respective related control information stored in the memory, the memory being configured to permit retrieval, at a second clock rate used in the second clock domain, of the respective data, the respective related control information, and the respective identification information stored in the memory.