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AssigneeHitachi, Ltd.
InventorYuki Kondoh
Estimating the term…
A processor and its arithmetic instruction processing method and arithmetic operation control method are disclosed that add a new operand designation option to SIMD arithmetic instructions and permit software pipelining between arithmetic operations performed in parallel by a SIMD arithmetic unit. A selector for adding an operation for interchanging multiple outputs of a SIMD arithmetic unit is added to a data path. A register file is divided in accordance with the output bit fields of the SIMD arithmetic unit. A means of specifying multiple registers as a SIMD instruction's output operand is added. Therefore, part of the output results of arithmetic operations performed in parallel by the SIMD arithmetic unit can be stored in a register providing the input for another arithmetic operation. Software pipelining is rendered achievable in this manner.
A processor comprising:
A processor equipped with a plurality of registers, an arithmetic operation circuit, a plurality of control signals, a first input flip-flop, a second input flip-flop, and a plurality of output flip-flops, wherein said processor performs a first arithmetic operation on first data in a first part of said first input flip-flop, said first data previously entered in said first input flip-flop from a first one of said plurality of registers, and second data in a first part of said second input flip-flop, said second data previously entered in said second input flip-flop from a second one of said plurality of registers, in accordance with an arithmetic instruction in said arithmetic operation circuit;
A processor comprising;
Dependencies are inferred from the claim text.