Non-temporal memory reference control mechanism

An apparatus, for adding instruction level non-temporal access control features to an existing instruction set, the apparatus comprising:

• an escape tag, for reception by translation logic, and for indicating that accompanying parts of a corresponding instruction prescribe a memory reference, wherein said escape tag is a first opcode within the existing instruction set;
• a non-temporal access specifier, coupled to said escape tag and being one of said accompanying parts, for prescribing that a non-temporal access be employed to perform said memory reference;
• and
• extended execution logic, coupled to said translation logic, for executing said memory reference via said non-temporal access.

A method for extending an existing instruction set architecture to provide for non-temporal memory reference control at the instruction level, the method comprising:

• providing an extended instruction, the extended instruction including an extended tag along with an extended prefix, wherein the extended tag is a first opcode entity according to the existing instruction set architecture;
• prescribing, via the extended prefix, that a non-temporal access be employed for a corresponding memory reference, wherein the memory reference is specified by remaining parts of the extended instruction;
• and
• employing the non-temporal access to execute the memory reference, wherein said employing precludes caching of data corresponding to the memory reference.